soc/interconnect: add stream_sim
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ba959c832d
commit
032f5a9620
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@ -0,0 +1,193 @@
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import random
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import math
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from copy import deepcopy
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from litex.gen import *
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from litex.soc.interconnect.stream import Sink, Source
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def print_with_prefix(s, prefix=""):
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if not isinstance(s, str):
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s = s.__repr__()
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s = s.split("\n")
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for l in s:
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print(prefix + l)
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def seed_to_data(seed, random=True):
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if random:
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return (seed * 0x31415979 + 1) & 0xffffffff
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else:
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return seed
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def split_bytes(v, n, endianness="big"):
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r = []
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r_bytes = v.to_bytes(n, byteorder=endianness)
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for byte in r_bytes:
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r.append(int(byte))
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return r
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def merge_bytes(b, endianness="big"):
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return int.from_bytes(bytes(b), endianness)
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def get_field_data(field, datas):
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v = merge_bytes(datas[field.byte:field.byte+math.ceil(field.width/8)])
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return (v >> field.offset) & (2**field.width-1)
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def comp(p1, p2):
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r = True
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for x, y in zip(p1, p2):
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if x != y:
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r = False
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return r
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def check(p1, p2):
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p1 = deepcopy(p1)
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p2 = deepcopy(p2)
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if isinstance(p1, int):
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return 0, 1, int(p1 != p2)
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else:
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if len(p1) >= len(p2):
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ref, res = p1, p2
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else:
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ref, res = p2, p1
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shift = 0
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while((ref[0] != res[0]) and (len(res) > 1)):
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res.pop(0)
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shift += 1
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length = min(len(ref), len(res))
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errors = 0
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for i in range(length):
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if ref.pop(0) != res.pop(0):
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errors += 1
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return shift, length, errors
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def randn(max_n):
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return random.randint(0, max_n-1)
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class RandRun:
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def __init__(self, level=0):
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self.run = True
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self.level = level
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def do_simulation(self, selfp):
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self.run = True
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n = randn(100)
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if n < self.level:
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self.run = False
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class Packet(list):
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def __init__(self, init=[]):
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self.ongoing = False
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self.done = False
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for data in init:
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self.append(data)
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class PacketStreamer(Module):
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def __init__(self, description, last_be=None):
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self.source = Source(description)
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self.last_be = last_be
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# # #
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self.packets = []
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self.packet = Packet()
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self.packet.done = True
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def send(self, packet):
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packet = deepcopy(packet)
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self.packets.append(packet)
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return packet
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def send_blocking(self, packet):
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packet = self.send(packet)
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while not packet.done:
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yield
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def do_simulation(self, selfp):
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if len(self.packets) and self.packet.done:
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self.packet = self.packets.pop(0)
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if not self.packet.ongoing and not self.packet.done:
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selfp.source.stb = 1
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if self.source.description.packetized:
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selfp.source.sop = 1
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selfp.source.data = self.packet.pop(0)
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self.packet.ongoing = True
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elif selfp.source.stb == 1 and selfp.source.ack == 1:
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if self.source.description.packetized:
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selfp.source.sop = 0
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if len(self.packet) == 1:
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selfp.source.eop = 1
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if self.last_be is not None:
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selfp.source.last_be = self.last_be
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else:
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selfp.source.eop = 0
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if self.last_be is not None:
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selfp.source.last_be = 0
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if len(self.packet) > 0:
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selfp.source.stb = 1
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selfp.source.data = self.packet.pop(0)
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else:
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self.packet.done = True
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selfp.source.stb = 0
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class PacketLogger(Module):
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def __init__(self, description):
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self.sink = Sink(description)
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# # #
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self.packet = Packet()
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def receive(self):
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self.packet.done = False
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while not self.packet.done:
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yield
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def do_simulation(self, selfp):
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selfp.sink.ack = 1
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if selfp.sink.stb:
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if self.sink.description.packetized:
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if selfp.sink.sop:
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self.packet = Packet()
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self.packet.append(selfp.sink.data)
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else:
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self.packet.append(selfp.sink.data)
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if selfp.sink.eop:
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self.packet.done = True
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else:
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self.packet.append(selfp.sink.data)
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class AckRandomizer(Module):
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def __init__(self, description, level=0):
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self.level = level
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self.sink = Sink(description)
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self.source = Source(description)
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self.run = Signal()
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self.comb += \
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If(self.run,
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Record.connect(self.sink, self.source)
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).Else(
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self.source.stb.eq(0),
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self.sink.ack.eq(0),
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)
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def do_simulation(self, selfp):
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n = randn(100)
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if n < self.level:
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selfp.run = 0
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else:
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selfp.run = 1
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@ -13,7 +13,7 @@ from litex.soc.interconnect.stream import Sink, Source
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class Counter(Module):
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def __init__(self, *args, increment=1, **kwargs):
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self.value = Signal(*args, **kwargs)
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self.width = flen(self.value)
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self.width = len(self.value)
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self.sync += self.value.eq(self.value+increment)
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@ -107,7 +107,7 @@ class WishboneStreamingBridge(Module):
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self.comb += [
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self.wishbone.adr.eq(address + word_counter.value),
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self.wishbone.dat_w.eq(data),
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self.wishbone.sel.eq(2**flen(self.wishbone.sel)-1)
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self.wishbone.sel.eq(2**len(self.wishbone.sel)-1)
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]
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fsm.act("WRITE_DATA",
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self.wishbone.stb.eq(1),
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