soc/integration/cpu_interface: generate name for Memories in get_csr_header

2019-01-05 10:57:37 +01:00 · 2019-01-05 10:57:37 +01:00 · 041bf41226
parent 9f5d0cef6b
commit 041bf41226
1 changed files with 1 additions and 0 deletions
--- a/litex/soc/integration/cpu_interface.py
+++ b/litex/soc/integration/cpu_interface.py
@ -137,6 +137,7 @@ def get_csr_header(regions, constants, with_access_functions=True, with_shadow_b
        if not with_shadow_base:
            origin &= (~shadow_base)
        if isinstance(obj, Memory):
+            r += "\n/* "+name+" */\n"
            r += "#define CSR_"+name.upper()+"_BASE "+hex(origin)+"\n"
        else:
            r += "\n/* "+name+" */\n"