test/support,signed,sort: use new simulator

migen/test/support.py

@@ -1,24 +1,14 @@
 from migen.fhdl.std import *
-from migen.sim.generic import run_simulation
+from migen.sim import Simulator
 from migen.fhdl import verilog
 
 
-class SimBench(Module):
-    callback = None
-    def do_simulation(self, selfp):
-        if self.callback is not None:
-            return self.callback(self, selfp)
-
-
 class SimCase:
-    TestBench = SimBench
-
     def setUp(self, *args, **kwargs):
         self.tb = self.TestBench(*args, **kwargs)
 
     def test_to_verilog(self):
         verilog.convert(self.tb)
 
-    def run_with(self, cb, ncycles=None):
-        self.tb.callback = cb
-        run_simulation(self.tb, ncycles=ncycles)
+    def run_with(self, generator):
+        Simulator(self.tb, generator).run()

migen/test/test_signed.py

@@ -1,11 +1,11 @@
 import unittest
 
 from migen.fhdl.std import *
-from migen.test.support import SimCase, SimBench
+from migen.test.support import SimCase
 
 
 class SignedCase(SimCase, unittest.TestCase):
-    class TestBench(SimBench):
+    class TestBench(Module):
         def __init__(self):
             self.a = Signal((3, True))
             self.b = Signal((4, True))
@@ -27,20 +27,16 @@ class SignedCase(SimCase, unittest.TestCase):
                         self.vals.append((asign, bsign, f, r, r0.op))
 
     def test_comparisons(self):
-        values = range(-4, 4)
-        agen = iter(values)
-        bgen = iter(values)
-        def cb(tb, tbp):
-            try:
-                tbp.a = next(agen)
-                tbp.b = next(bgen)
-            except StopIteration:
-                raise StopSimulation
-            a = tbp.a
-            b = tbp.b
-            for asign, bsign, f, r, op in self.tb.vals:
-                r, r0 = tbp.simulator.rd(r), f(asign*a, bsign*b)
-                self.assertEqual(r, int(r0),
-                        "got {}, want {}*{} {} {}*{} = {}".format(
-                            r, asign, a, op, bsign, b, r0))
-        self.run_with(cb)
+        def gen():
+            for i in range(-4, 4):
+                yield self.tb.a, i
+                yield self.tb.b, i
+                a = yield self.tb.a
+                b = yield self.tb.b
+                for asign, bsign, f, r, op in self.tb.vals:
+                    r, r0 = (yield r), f(asign*a, bsign*b)
+                    self.assertEqual(r, int(r0),
+                            "got {}, want {}*{} {} {}*{} = {}".format(
+                                r, asign, a, op, bsign, b, r0))
+                yield
+        self.run_with(gen())

migen/test/test_sort.py

@@ -4,11 +4,11 @@ from random import randrange
 from migen.fhdl.std import *
 from migen.genlib.sort import *
 
-from migen.test.support import SimCase, SimBench
+from migen.test.support import SimCase
 
 
 class BitonicCase(SimCase, unittest.TestCase):
-    class TestBench(SimBench):
+    class TestBench(Module):
         def __init__(self):
             self.submodules.dut = BitonicSort(8, 4, ascending=True)
 
@@ -20,8 +20,11 @@ class BitonicCase(SimCase, unittest.TestCase):
             self.assertEqual(flen(self.tb.dut.o[i]), 4)
 
     def test_sort(self):
-        def cb(tb, tbp):
-            for i in tb.dut.i:
-                tbp.simulator.wr(i, randrange(1<<flen(i)))
-            self.assertEqual(sorted(list(tbp.dut.i)), list(tbp.dut.o))
-        self.run_with(cb, 20)
+        def gen():
+            for repeat in range(20):
+                for i in self.tb.dut.i:
+                    yield i, randrange(1<<flen(i))
+                yield
+                self.assertEqual(sorted((yield self.tb.dut.i)),
+                                 (yield self.tb.dut.o))
+        self.run_with(gen())