bus: simplify and cleanup
Unify slave and master interfaces Remove signal direction suffixes Generic simple interconnect Wishbone point-to-point interconnect Description filter (get_name) Misc cleanups
This commit is contained in:
Sebastien Bourdeauducq
parent
46b1f74e98
commit
0493212124
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@ -1,10 +1,10 @@
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from migen.fhdl import verilog
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from migen.bus import wishbone
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m1 = wishbone.Master()
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m2 = wishbone.Master()
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s1 = wishbone.Slave()
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s2 = wishbone.Slave()
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m1 = wishbone.Interface()
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m2 = wishbone.Interface()
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s1 = wishbone.Interface()
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s2 = wishbone.Interface()
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wishbonecon0 = wishbone.InterconnectShared(
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[m1, m2],
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[(0, s1), (1, s2)],
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@ -12,8 +12,8 @@ wishbonecon0 = wishbone.InterconnectShared(
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offset=1)
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frag = wishbonecon0.get_fragment()
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v = verilog.convert(frag, name="intercon", ios={m1.cyc_o, m1.stb_o, m1.we_o, m1.adr_o, m1.sel_o, m1.dat_o, m1.dat_i, m1.ack_i,
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m2.cyc_o, m2.stb_o, m2.we_o, m2.adr_o, m2.sel_o, m2.dat_o, m2.dat_i, m2.ack_i,
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s1.cyc_i, s1.stb_i, s1.we_i, s1.adr_i, s1.sel_i, s1.dat_i, s1.dat_o, s1.ack_o,
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s2.cyc_i, s2.stb_i, s2.we_i, s2.adr_i, s2.sel_i, s2.dat_i, s2.dat_o, s2.ack_o})
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v = verilog.convert(frag, name="intercon", ios={m1.cyc, m1.stb, m1.we, m1.adr, m1.sel, m1.dat_w, m1.dat_r, m1.ack,
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m2.cyc, m2.stb, m2.we, m2.adr, m2.sel, m2.dat_r, m2.dat_w, m2.ack,
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s1.cyc, s1.stb, s1.we, s1.adr, s1.sel, s1.dat_r, s1.dat_w, s1.ack,
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s2.cyc, s2.stb, s2.we, s2.adr, s2.sel, s2.dat_r, s2.dat_w, s2.ack})
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print(v)
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@ -80,42 +80,42 @@ intercon dut(
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.sys_rst(sys_rst),
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// Master 0
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.m1_wishbone_dat_o(m1_wishbone_dat_w),
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.m1_wishbone_dat_i(m1_wishbone_dat_r),
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.m1_wishbone_adr_o(m1_wishbone_adr),
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.m1_wishbone_we_o(m1_wishbone_we),
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.m1_wishbone_sel_o(m1_wishbone_sel),
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.m1_wishbone_cyc_o(m1_wishbone_cyc),
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.m1_wishbone_stb_o(m1_wishbone_stb),
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.m1_wishbone_ack_i(m1_wishbone_ack),
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.m1_wishbone_dat_w(m1_wishbone_dat_w),
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.m1_wishbone_dat_r(m1_wishbone_dat_r),
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.m1_wishbone_adr(m1_wishbone_adr),
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.m1_wishbone_we(m1_wishbone_we),
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.m1_wishbone_sel(m1_wishbone_sel),
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.m1_wishbone_cyc(m1_wishbone_cyc),
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.m1_wishbone_stb(m1_wishbone_stb),
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.m1_wishbone_ack(m1_wishbone_ack),
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// Master 1
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.m2_wishbone_dat_o(m2_wishbone_dat_w),
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.m2_wishbone_dat_i(m2_wishbone_dat_r),
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.m2_wishbone_adr_o(m2_wishbone_adr),
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.m2_wishbone_we_o(m2_wishbone_we),
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.m2_wishbone_sel_o(m2_wishbone_sel),
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.m2_wishbone_cyc_o(m2_wishbone_cyc),
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.m2_wishbone_stb_o(m2_wishbone_stb),
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.m2_wishbone_ack_i(m2_wishbone_ack),
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.m2_wishbone_dat_w(m2_wishbone_dat_w),
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.m2_wishbone_dat_r(m2_wishbone_dat_r),
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.m2_wishbone_adr(m2_wishbone_adr),
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.m2_wishbone_we(m2_wishbone_we),
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.m2_wishbone_sel(m2_wishbone_sel),
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.m2_wishbone_cyc(m2_wishbone_cyc),
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.m2_wishbone_stb(m2_wishbone_stb),
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.m2_wishbone_ack(m2_wishbone_ack),
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// Slave 0
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.s1_wishbone_dat_o(s1_wishbone_dat_r),
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.s1_wishbone_dat_i(s1_wishbone_dat_w),
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.s1_wishbone_adr_i(s1_wishbone_adr),
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.s1_wishbone_sel_i(s1_wishbone_sel),
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.s1_wishbone_we_i(s1_wishbone_we),
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.s1_wishbone_cyc_i(s1_wishbone_cyc),
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.s1_wishbone_stb_i(s1_wishbone_stb),
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.s1_wishbone_ack_o(s1_wishbone_ack),
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.s1_wishbone_dat_r(s1_wishbone_dat_r),
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.s1_wishbone_dat_w(s1_wishbone_dat_w),
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.s1_wishbone_adr(s1_wishbone_adr),
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.s1_wishbone_sel(s1_wishbone_sel),
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.s1_wishbone_we(s1_wishbone_we),
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.s1_wishbone_cyc(s1_wishbone_cyc),
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.s1_wishbone_stb(s1_wishbone_stb),
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.s1_wishbone_ack(s1_wishbone_ack),
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// Slave 1
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.s2_wishbone_dat_o(s2_wishbone_dat_r),
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.s2_wishbone_dat_i(s2_wishbone_dat_w),
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.s2_wishbone_adr_i(s2_wishbone_adr),
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.s2_wishbone_sel_i(s2_wishbone_sel),
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.s2_wishbone_we_i(s2_wishbone_we),
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.s2_wishbone_cyc_i(s2_wishbone_cyc),
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.s2_wishbone_stb_i(s2_wishbone_stb),
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.s2_wishbone_ack_o(s2_wishbone_ack)
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.s2_wishbone_dat_r(s2_wishbone_dat_r),
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.s2_wishbone_dat_w(s2_wishbone_dat_w),
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.s2_wishbone_adr(s2_wishbone_adr),
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.s2_wishbone_sel(s2_wishbone_sel),
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.s2_wishbone_we(s2_wishbone_we),
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.s2_wishbone_cyc(s2_wishbone_cyc),
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.s2_wishbone_stb(s2_wishbone_stb),
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.s2_wishbone_ack(s2_wishbone_ack)
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);
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//---------------------------------------------------------------------------
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@ -1,33 +1,16 @@
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from migen.fhdl.structure import *
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from migen.corelogic.misc import optree
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from migen.bus.simple import Simple
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from migen.bus.simple import *
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_desc = [
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(True, "adr", 14),
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(True, "we", 1),
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(True, "dat", 8),
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(False, "dat", 8)
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]
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_desc = Description(
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(M_TO_S, "adr", 14),
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(M_TO_S, "we", 1),
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(M_TO_S, "dat_w", 8),
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(S_TO_M, "dat_r", 8)
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)
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class Master(Simple):
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class Interface(SimpleInterface):
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def __init__(self):
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Simple.__init__(self, _desc, False)
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SimpleInterface.__init__(self, _desc)
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class Slave(Simple):
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def __init__(self):
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Simple.__init__(self, _desc, True)
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class Interconnect:
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def __init__(self, master, slaves):
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self.master = master
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self.slaves = slaves
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def get_fragment(self):
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comb = []
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for slave in self.slaves:
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comb.append(slave.adr_i.eq(self.master.adr_o))
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comb.append(slave.we_i.eq(self.master.we_o))
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comb.append(slave.dat_i.eq(self.master.dat_o))
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rb = optree("|", [slave.dat_o for slave in self.slaves])
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comb.append(self.master.dat_i.eq(rb))
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return Fragment(comb)
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class Interconnect(SimpleInterconnect):
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pass
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@ -1,25 +1,44 @@
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from migen.fhdl.structure import *
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from migen.corelogic.misc import optree
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def get_sig_name(signal, slave):
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if signal[0] ^ slave:
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suffix = "_o"
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else:
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suffix = "_i"
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return signal[1] + suffix
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(S_TO_M, M_TO_S) = range(2)
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# desc is a list of tuples, each made up of:
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# 0) boolean: "master to slave"
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# 0) S_TO_M/M_TO_S: data direction
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# 1) string: name
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# 2) int: width
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class Simple():
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def __init__(self, desc, slave):
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for signal in desc:
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class Description:
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def __init__(self, *desc):
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self.desc = desc
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def get_names(self, direction, *exclude_list):
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exclude = set(exclude_list)
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return [signal[1]
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for signal in self.desc
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if signal[0] == direction and signal[1] not in exclude]
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class SimpleInterface:
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def __init__(self, desc):
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self.desc = desc
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modules = self.__module__.split(".")
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busname = modules[len(modules)-1]
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signame = get_sig_name(signal, slave)
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for signal in self.desc.desc:
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signame = signal[1]
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setattr(self, signame, Signal(BV(signal[2]), busname + "_" + signame))
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def signals(self):
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return [self.__dict__[k]
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for k in self.__dict__
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if isinstance(self.__dict__[k], Signal)]
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class SimpleInterconnect:
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def __init__(self, master, slaves):
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self.master = master
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self.slaves = slaves
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def get_fragment(self):
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s2m = master.desc.get_names(S_TO_M)
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m2s = master.desc.get_names(M_TO_S)
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comb = [getattr(slave, name).eq(getattr(master, name))
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for name in m2s for slave in self.slave]
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comb += [getattr(master, name).eq(
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optree("|", [getattr(slave, name) for slave in self.slaves])
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)
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for name in s2m]
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return Fragment(comb)
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@ -1,29 +1,29 @@
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from migen.fhdl.structure import *
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from migen.corelogic import roundrobin
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from migen.corelogic.misc import multimux, optree
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from migen.bus.simple import Simple, get_sig_name
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from migen.bus.simple import *
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_desc = [
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(True, "adr", 30),
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(True, "dat", 32),
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(False, "dat", 32),
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(True, "sel", 4),
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(True, "cyc", 1),
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(True, "stb", 1),
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(False, "ack", 1),
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(True, "we", 1),
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(True, "cti", 3),
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(True, "bte", 2),
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(False, "err", 1)
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]
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_desc = Description(
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(M_TO_S, "adr", 30),
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(M_TO_S, "dat_w", 32),
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(S_TO_M, "dat_r", 32),
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(M_TO_S, "sel", 4),
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(M_TO_S, "cyc", 1),
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(M_TO_S, "stb", 1),
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(S_TO_M, "ack", 1),
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(M_TO_S, "we", 1),
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(M_TO_S, "cti", 3),
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(M_TO_S, "bte", 2),
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(S_TO_M, "err", 1)
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)
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class Master(Simple):
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class Interface(SimpleInterface):
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def __init__(self):
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Simple.__init__(self, _desc, False)
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SimpleInterface.__init__(self, _desc)
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class Slave(Simple):
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def __init__(self):
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Simple.__init__(self, _desc, True)
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class InterconnectPointToPoint(SimpleInterconnect):
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def __init__(self, master, slave):
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SimpleInterconnect.__init__(self, master, [slave])
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class Arbiter:
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def __init__(self, masters, target):
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@ -35,26 +35,23 @@ class Arbiter:
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comb = []
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# mux master->slave signals
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m2s_names = [get_sig_name(x, False) for x in _desc if x[0]]
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m2s_names = _desc.get_names(M_TO_S)
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m2s_masters = [[getattr(m, name) for name in m2s_names] for m in self.masters]
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m2s_target = [getattr(self.target, name) for name in m2s_names]
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comb += multimux(self.rr.grant, m2s_masters, m2s_target)
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# connect slave->master signals
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s2m_names = [get_sig_name(x, False) for x in _desc if not x[0]]
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for name in s2m_names:
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for name in _desc.get_names(S_TO_M):
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source = getattr(self.target, name)
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i = 0
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for m in self.masters:
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for i, m in enumerate(self.masters):
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dest = getattr(m, name)
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if name == "ack_i" or name == "err_i":
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if name == "ack" or name == "err":
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comb.append(dest.eq(source & (self.rr.grant == Constant(i, self.rr.grant.bv))))
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else:
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comb.append(dest.eq(source))
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i += 1
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# connect bus requests to round-robin selector
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reqs = [m.cyc_o for m in self.masters]
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reqs = [m.cyc for m in self.masters]
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comb.append(self.rr.request.eq(Cat(*reqs)))
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return Fragment(comb) + self.rr.get_fragment()
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@ -92,42 +89,38 @@ class Decoder:
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slave_sel_r = Signal(BV(ns))
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# decode slave addresses
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i = 0
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hi = self.master.adr_o.bv.width - self.offset
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for addr in self.addresses:
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comb.append(slave_sel[i].eq(
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self.master.adr_o[hi-addr.bv.width:hi] == addr))
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i += 1
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hi = self.master.adr.bv.width - self.offset
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comb += [slave_sel[i].eq(self.master.adr[hi-addr.bv.width:hi] == addr)
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for i, addr in enumerate(self.addresses)]
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if self.register:
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sync.append(slave_sel_r.eq(slave_sel))
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else:
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comb.append(slave_sel_r.eq(slave_sel))
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# connect master->slaves signals except cyc
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m2s_names = [(get_sig_name(x, False), get_sig_name(x, True))
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for x in _desc if x[0] and x[1] != "cyc"]
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comb += [getattr(slave[1], name[1]).eq(getattr(self.master, name[0]))
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m2s_names = _desc.get_names(M_TO_S, "cyc")
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comb += [getattr(slave[1], name).eq(getattr(self.master, name))
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for name in m2s_names for slave in self.slaves]
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# combine cyc with slave selection signals
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i = 0
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for slave in self.slaves:
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comb.append(slave[1].cyc_i.eq(self.master.cyc_o & slave_sel[i]))
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i += 1
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comb += [slave[1].cyc.eq(self.master.cyc & slave_sel[i])
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for i, slave in enumerate(self.slaves)]
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# generate master ack (resp. err) by ORing all slave acks (resp. errs)
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comb.append(self.master.ack_i.eq(optree("|", [slave[1].ack_o for slave in self.slaves])))
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comb.append(self.master.err_i.eq(optree("|", [slave[1].err_o for slave in self.slaves])))
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comb += [
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self.master.ack.eq(optree("|", [slave[1].ack for slave in self.slaves])),
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self.master.err.eq(optree("|", [slave[1].err for slave in self.slaves]))
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]
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# mux (1-hot) slave data return
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masked = [Replicate(slave_sel_r[i], self.master.dat_i.bv.width) & self.slaves[i][1].dat_o for i in range(len(self.slaves))]
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comb.append(self.master.dat_i.eq(optree("|", masked)))
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masked = [Replicate(slave_sel_r[i], self.master.dat_r.bv.width) & self.slaves[i][1].dat_r for i in range(len(self.slaves))]
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comb.append(self.master.dat_r.eq(optree("|", masked)))
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return Fragment(comb, sync)
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class InterconnectShared:
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def __init__(self, masters, slaves, offset=0, register=False):
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self._shared = Master()
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self._shared = Interface()
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self._arbiter = Arbiter(masters, self._shared)
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self._decoder = Decoder(self._shared, slaves, offset, register)
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self.addresses = self._decoder.addresses
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@ -18,7 +18,7 @@ def _log2_int(n):
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# cachesize (in 32-bit words) is the size of the data store, must be a power of 2
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class WB2ASMI:
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def __init__(self, cachesize, asmiport):
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self.wishbone = wishbone.Slave()
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self.wishbone = wishbone.Interface()
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self.cachesize = cachesize
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self.asmiport = asmiport
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if len(self.asmiport.slots) != 1:
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@ -41,7 +41,7 @@ class WB2ASMI:
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addressbits = aaw + offsetbits
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linebits = _log2_int(self.cachesize) - offsetbits
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tagbits = aaw - linebits
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adr_offset, adr_line, adr_tag = split(self.wishbone.adr_i, offsetbits, linebits, tagbits)
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adr_offset, adr_line, adr_tag = split(self.wishbone.adr, offsetbits, linebits, tagbits)
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# Data memory
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data_adr = Signal(BV(linebits))
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|
|
@ -60,16 +60,16 @@ class WB2ASMI:
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data_di.eq(self.asmiport.dat_r),
|
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data_we.eq(Replicate(1, adw//8))
|
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).Else(
|
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data_di.eq(Replicate(self.wishbone.dat_i, adw//32)),
|
||||
If(self.wishbone.cyc_i & self.wishbone.stb_i & self.wishbone.we_i & self.wishbone.ack_o,
|
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displacer(self.wishbone.sel_i, adr_offset, data_we, 2**offsetbits, reverse=True)
|
||||
data_di.eq(Replicate(self.wishbone.dat_w, adw//32)),
|
||||
If(self.wishbone.cyc & self.wishbone.stb & self.wishbone.we & self.wishbone.ack,
|
||||
displacer(self.wishbone.sel, adr_offset, data_we, 2**offsetbits, reverse=True)
|
||||
)
|
||||
),
|
||||
If(write_to_asmi,
|
||||
self.asmiport.dat_w.eq(data_do),
|
||||
self.asmiport.dat_wm.eq(Replicate(1, adw//8))
|
||||
),
|
||||
chooser(data_do, adr_offset_r, self.wishbone.dat_o, reverse=True)
|
||||
chooser(data_do, adr_offset_r, self.wishbone.dat_r, reverse=True)
|
||||
]
|
||||
sync += [
|
||||
adr_offset_r.eq(adr_offset)
|
||||
|
|
@ -102,12 +102,12 @@ class WB2ASMI:
|
|||
"REFILL_WRTAG", "REFILL_ISSUE", "REFILL_WAIT", "REFILL_COMPLETE")
|
||||
|
||||
fsm.act(fsm.IDLE,
|
||||
If(self.wishbone.cyc_i & self.wishbone.stb_i, fsm.next_state(fsm.TEST_HIT))
|
||||
If(self.wishbone.cyc & self.wishbone.stb, fsm.next_state(fsm.TEST_HIT))
|
||||
)
|
||||
fsm.act(fsm.TEST_HIT,
|
||||
If(tag_do.tag == adr_tag,
|
||||
self.wishbone.ack_o.eq(1),
|
||||
If(self.wishbone.we_i,
|
||||
self.wishbone.ack.eq(1),
|
||||
If(self.wishbone.we,
|
||||
tag_di.dirty.eq(1),
|
||||
tag_we.eq(1)
|
||||
),
|
||||
|
|
|
|||
|
|
@ -5,18 +5,18 @@ from migen.corelogic import timeline
|
|||
|
||||
class WB2CSR:
|
||||
def __init__(self):
|
||||
self.wishbone = wishbone.Slave()
|
||||
self.csr = csr.Master()
|
||||
self.timeline = timeline.Timeline(self.wishbone.cyc_i & self.wishbone.stb_i,
|
||||
[(1, [self.csr.we_o.eq(self.wishbone.we_i)]),
|
||||
(2, [self.wishbone.ack_o.eq(1)]),
|
||||
(3, [self.wishbone.ack_o.eq(0)])])
|
||||
self.wishbone = wishbone.Interface()
|
||||
self.csr = csr.Interface()
|
||||
self.timeline = timeline.Timeline(self.wishbone.cyc & self.wishbone.stb,
|
||||
[(1, [self.csr.we.eq(self.wishbone.we)]),
|
||||
(2, [self.wishbone.ack.eq(1)]),
|
||||
(3, [self.wishbone.ack.eq(0)])])
|
||||
|
||||
def get_fragment(self):
|
||||
sync = [
|
||||
self.csr.we_o.eq(0),
|
||||
self.csr.dat_o.eq(self.wishbone.dat_i[:8]),
|
||||
self.csr.adr_o.eq(self.wishbone.adr_i[:14]),
|
||||
self.wishbone.dat_o.eq(self.csr.dat_i)
|
||||
self.csr.we.eq(0),
|
||||
self.csr.dat_w.eq(self.wishbone.dat_w[:8]),
|
||||
self.csr.adr.eq(self.wishbone.adr[:14]),
|
||||
self.wishbone.dat_r.eq(self.csr.dat_r)
|
||||
]
|
||||
return Fragment(sync=sync) + self.timeline.get_fragment()
|
||||
|
|
|
|||
Loading…
Reference in New Issue