soc/csr_bus: improve CSR paging genericity
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351896bf57
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0497f3ca71
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@ -428,11 +428,11 @@ class SoCCSRHandler(SoCLocHandler):
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supported_data_width = [8, 32]
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supported_data_width = [8, 32]
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supported_address_width = [14, 15]
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supported_address_width = [14, 15]
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supported_alignment = [32, 64]
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supported_alignment = [32, 64]
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supported_paging = [0x800, 0x1000]
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supported_paging = [0x800*2**i for i in range(3)]
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# Creation -------------------------------------------------------------------------------------
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# Creation -------------------------------------------------------------------------------------
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def __init__(self, data_width=32, address_width=14, alignment=32, paging=0x800, reserved_csrs={}):
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def __init__(self, data_width=32, address_width=14, alignment=32, paging=0x800, reserved_csrs={}):
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SoCLocHandler.__init__(self, "CSR", n_locs=4*2**address_width//paging) # FIXME
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SoCLocHandler.__init__(self, "CSR", n_locs=alignment//8*(2**address_width)//paging)
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self.logger = logging.getLogger("SoCCSRHandler")
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self.logger = logging.getLogger("SoCCSRHandler")
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self.logger.info("Creating CSR Handler...")
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self.logger.info("Creating CSR Handler...")
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@ -468,10 +468,10 @@ class SoCCSRHandler(SoCLocHandler):
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# Check Paging
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# Check Paging
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if paging not in self.supported_paging:
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if paging not in self.supported_paging:
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self.logger.error("Unsupported {} {}, supporteds: {:s}".format(
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self.logger.error("Unsupported {} 0x{}, supporteds: {:s}".format(
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colorer("Paging", color="red"),
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colorer("Paging", color="red"),
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colorer(paging),
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colorer("{:x}".format(paging)),
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colorer(", ".join(str(x) for x in self.supported_paging))))
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colorer(", ".join("0x{:x}".format(x) for x in self.supported_paging))))
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raise
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raise
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# Create CSR Handler
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# Create CSR Handler
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@ -78,22 +78,23 @@ class InterconnectShared(Module):
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class SRAM(Module):
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class SRAM(Module):
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def __init__(self, mem_or_size, address, paging=0x800, read_only=None, init=None, bus=None):
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def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None, paging=0x800):
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if bus is None:
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if bus is None:
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bus = Interface()
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bus = Interface()
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self.bus = bus
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self.bus = bus
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aligned_paging = paging//(bus.alignment//8)
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data_width = len(self.bus.dat_w)
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data_width = len(self.bus.dat_w)
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if isinstance(mem_or_size, Memory):
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if isinstance(mem_or_size, Memory):
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mem = mem_or_size
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mem = mem_or_size
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else:
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else:
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mem = Memory(data_width, mem_or_size//(data_width//8), init=init)
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mem = Memory(data_width, mem_or_size//(data_width//8), init=init)
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mem_size = int(mem.width*mem.depth/8)
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mem_size = int(mem.width*mem.depth/8)
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if mem_size > paging//4:
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if mem_size > aligned_paging:
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print("WARNING: memory > {} bytes in CSR region requires paged access (mem_size = {} bytes)".format(
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print("WARNING: memory > {} bytes in CSR region requires paged access (mem_size = {} bytes)".format(
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paging//4, mem_size))
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paging//4, mem_size))
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csrw_per_memw = (mem.width + data_width - 1)//data_width
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csrw_per_memw = (mem.width + data_width - 1)//data_width
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word_bits = log2_int(csrw_per_memw)
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word_bits = log2_int(csrw_per_memw)
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page_bits = log2_int((mem.depth*csrw_per_memw + paging//4 - 1)//(paging//4), False)
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page_bits = log2_int((mem.depth*csrw_per_memw + aligned_paging - 1)//aligned_paging, False)
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if page_bits:
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if page_bits:
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self._page = CSRStorage(page_bits, name=mem.name_override + "_page")
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self._page = CSRStorage(page_bits, name=mem.name_override + "_page")
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else:
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else:
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@ -112,7 +113,7 @@ class SRAM(Module):
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sel = Signal()
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sel = Signal()
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sel_r = Signal()
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sel_r = Signal()
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self.sync += sel_r.eq(sel)
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self.sync += sel_r.eq(sel)
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self.comb += sel.eq(self.bus.adr[log2_int(paging//4):] == address)
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self.comb += sel.eq(self.bus.adr[log2_int(aligned_paging):] == address)
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if bus.alignment == 64:
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if bus.alignment == 64:
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self.comb += If(self.bus.adr[0], sel.eq(0))
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self.comb += If(self.bus.adr[0], sel.eq(0))
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@ -165,13 +166,13 @@ class CSRBank(csr.GenericBank):
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if bus is None:
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if bus is None:
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bus = Interface()
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bus = Interface()
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self.bus = bus
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self.bus = bus
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aligned_paging = paging//(bus.alignment//8)
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###
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###
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csr.GenericBank.__init__(self, description, len(self.bus.dat_w))
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csr.GenericBank.__init__(self, description, len(self.bus.dat_w))
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sel = Signal()
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sel = Signal()
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self.comb += sel.eq(self.bus.adr[log2_int(paging//4):] == address)
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self.comb += sel.eq(self.bus.adr[log2_int(aligned_paging):] == address)
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if bus.alignment == 64:
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if bus.alignment == 64:
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self.comb += If(self.bus.adr[0], sel.eq(0))
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self.comb += If(self.bus.adr[0], sel.eq(0))
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