cores/xadc: Review/Cleanup PR#838, rename _XADC to SystemMonitorDRP and USSYSMON to USSystemMonitor.
This commit is contained in:
Florent Kermarrec
parent
367b510590
commit
04cb8e0e5e
|
|
@ -2,21 +2,24 @@
|
|||
# This file is part of LiteX.
|
||||
#
|
||||
# Copyright (c) 2014-2015 Robert Jordens <jordens@gmail.com>
|
||||
# Copyright (c) 2019-2021 Florent Kermarrec <florent@enjoy-digital.fr>
|
||||
# Copyright (c) 2019 bunnie <bunnie@kosagi.com>
|
||||
# Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
|
||||
# Copyright (c) 2021 Vamsi K Vytla <vamsi.vytla@gmail.com>
|
||||
# SPDX-License-Identifier: BSD-2-Clause
|
||||
|
||||
from migen import *
|
||||
|
||||
from litex.soc.interconnect.csr import *
|
||||
|
||||
# XADC ---------------------------------------------------------------------------------------------
|
||||
# Layouts -----------------------------------------------------------------------------------------
|
||||
|
||||
analog_layout = [("vauxp", 16), ("vauxn", 16), ("vp", 1), ("vn", 1)]
|
||||
|
||||
class _XADC(Module, AutoCSR):
|
||||
# Xilinx System Monitor DRP ------------------------------------------------------------------------
|
||||
|
||||
class SystemMonitorDRP(Module, AutoCSR):
|
||||
def expose_drp(self):
|
||||
self.drp_enable = CSRStorage() # Set to 1 to use DRP and disable auto-sampling
|
||||
self.drp_enable = CSRStorage() # Set to 1 to use DRP and disable auto-sampling.
|
||||
self.drp_read = CSR()
|
||||
self.drp_write = CSR()
|
||||
self.drp_drdy = CSRStatus()
|
||||
|
|
@ -26,7 +29,7 @@ class _XADC(Module, AutoCSR):
|
|||
|
||||
# # #
|
||||
|
||||
den_pipe = Signal() # add a register to ease timing closure of den
|
||||
den_pipe = Signal() # Add a register to ease timing closure of den.
|
||||
|
||||
self.comb += [
|
||||
self.di.eq(self.drp_dat_w.storage),
|
||||
|
|
@ -47,8 +50,9 @@ class _XADC(Module, AutoCSR):
|
|||
)
|
||||
]
|
||||
|
||||
# Xilinx 7-Series System Monitor -------------------------------------------------------------------
|
||||
|
||||
class XADC(_XADC, AutoCSR):
|
||||
class S7SystemMonitor(SystemMonitorDRP, AutoCSR):
|
||||
dadr_size = 7
|
||||
|
||||
def __init__(self, analog_pads=None):
|
||||
|
|
@ -79,7 +83,7 @@ class XADC(_XADC, AutoCSR):
|
|||
eoc = Signal()
|
||||
eos = Signal()
|
||||
|
||||
# XADC instance ----------------------------------------------------------------------------
|
||||
# XADC instance.
|
||||
self.dwe = Signal()
|
||||
self.den = Signal()
|
||||
self.drdy = Signal()
|
||||
|
|
@ -88,7 +92,7 @@ class XADC(_XADC, AutoCSR):
|
|||
self.do = Signal(16)
|
||||
self.drp_en = Signal()
|
||||
self.specials += Instance("XADC",
|
||||
# From ug480
|
||||
# From UG480
|
||||
p_INIT_40=0x9000, p_INIT_41=0x2ef0, p_INIT_42=0x0400,
|
||||
p_INIT_48=0x4701, p_INIT_49=0x000f,
|
||||
p_INIT_4A=0x4700, p_INIT_4B=0x0000,
|
||||
|
|
@ -127,12 +131,12 @@ class XADC(_XADC, AutoCSR):
|
|||
)
|
||||
]
|
||||
|
||||
# Channels update --------------------------------------------------------------------------
|
||||
# Channels update.
|
||||
channels = {
|
||||
0: self.temperature,
|
||||
1: self.vccint,
|
||||
2: self.vccaux,
|
||||
6: self.vccbram
|
||||
0x0 : self.temperature,
|
||||
0x1 : self.vccint,
|
||||
0x2 : self.vccaux,
|
||||
0x6 : self.vccbram
|
||||
}
|
||||
self.sync += [
|
||||
If(self.drdy,
|
||||
|
|
@ -142,14 +146,17 @@ class XADC(_XADC, AutoCSR):
|
|||
)
|
||||
]
|
||||
|
||||
# End of Convertion/Sequence update --------------------------------------------------------
|
||||
# End of Convertion/Sequence update.
|
||||
self.sync += [
|
||||
self.eoc.status.eq((self.eoc.status & ~self.eoc.we) | eoc),
|
||||
self.eos.status.eq((self.eos.status & ~self.eos.we) | eos),
|
||||
]
|
||||
|
||||
class XADC(S7SystemMonitor): pass
|
||||
|
||||
class USSYSMON(_XADC, AutoCSR):
|
||||
# Xilinx Ultrascale System Monitor -----------------------------------------------------------------
|
||||
|
||||
class USSystemMonitor(SystemMonitorDRP, AutoCSR):
|
||||
dadr_size = 8
|
||||
|
||||
def __init__(self, analog_pads=None):
|
||||
|
|
@ -186,7 +193,7 @@ class USSYSMON(_XADC, AutoCSR):
|
|||
eoc = Signal()
|
||||
eos = Signal()
|
||||
|
||||
# SYSMONE1 instance ----------------------------------------------------------------------------
|
||||
# SYSMONE1 instance ------------------------------------------------------------------------
|
||||
self.dwe = Signal()
|
||||
self.den = Signal()
|
||||
self.drdy = Signal()
|
||||
|
|
@ -195,7 +202,7 @@ class USSYSMON(_XADC, AutoCSR):
|
|||
self.do = Signal(16)
|
||||
self.drp_en = Signal()
|
||||
self.specials += Instance("SYSMONE1",
|
||||
# From ug580
|
||||
# From UG580
|
||||
p_INIT_40=0x9000, p_INIT_41=0x2fd0, p_INIT_42=0x1000,
|
||||
p_INIT_46=0x000f, p_INIT_48=0x4701, p_INIT_49=0x000f,
|
||||
p_INIT_47=0x000f, p_INIT_4A=0x47e0, p_INIT_4B=0x0000,
|
||||
|
|
@ -234,15 +241,15 @@ class USSYSMON(_XADC, AutoCSR):
|
|||
)
|
||||
]
|
||||
|
||||
# Channels update --------------------------------------------------------------------------
|
||||
# Channels update.
|
||||
channels = {
|
||||
0: self.temperature,
|
||||
1: self.vccint,
|
||||
2: self.vccaux,
|
||||
6: self.vccbram,
|
||||
0xd: self.vccpsintlp,
|
||||
0xe: self.vccpsintfp,
|
||||
0xf: self.vccpsaux,
|
||||
0x0 : self.temperature,
|
||||
0x1 : self.vccint,
|
||||
0x2 : self.vccaux,
|
||||
0x6 : self.vccbram,
|
||||
0xd : self.vccpsintlp,
|
||||
0xe : self.vccpsintfp,
|
||||
0xf : self.vccpsaux,
|
||||
}
|
||||
self.sync += [
|
||||
If(self.drdy,
|
||||
|
|
@ -252,7 +259,7 @@ class USSYSMON(_XADC, AutoCSR):
|
|||
)
|
||||
]
|
||||
|
||||
# End of Convertion/Sequence update --------------------------------------------------------
|
||||
# End of Convertion/Sequence update.
|
||||
self.sync += [
|
||||
self.eoc.status.eq((self.eoc.status & ~self.eoc.we) | eoc),
|
||||
self.eos.status.eq((self.eos.status & ~self.eos.we) | eos),
|
||||
|
|
|
|||
Loading…
Reference in New Issue