cores/xadc: Review/Cleanup PR#838, rename _XADC to SystemMonitorDRP and USSYSMON to USSystemMonitor.
This commit is contained in:
Florent Kermarrec
parent
367b510590
commit
04cb8e0e5e
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@ -2,21 +2,24 @@
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# This file is part of LiteX.
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#
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# Copyright (c) 2014-2015 Robert Jordens <jordens@gmail.com>
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# Copyright (c) 2019-2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2019 bunnie <bunnie@kosagi.com>
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# Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2021 Vamsi K Vytla <vamsi.vytla@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.soc.interconnect.csr import *
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# XADC ---------------------------------------------------------------------------------------------
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# Layouts -----------------------------------------------------------------------------------------
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analog_layout = [("vauxp", 16), ("vauxn", 16), ("vp", 1), ("vn", 1)]
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class _XADC(Module, AutoCSR):
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# Xilinx System Monitor DRP ------------------------------------------------------------------------
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class SystemMonitorDRP(Module, AutoCSR):
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def expose_drp(self):
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self.drp_enable = CSRStorage() # Set to 1 to use DRP and disable auto-sampling
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self.drp_enable = CSRStorage() # Set to 1 to use DRP and disable auto-sampling.
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self.drp_read = CSR()
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self.drp_write = CSR()
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self.drp_drdy = CSRStatus()
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@ -26,7 +29,7 @@ class _XADC(Module, AutoCSR):
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# # #
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den_pipe = Signal() # add a register to ease timing closure of den
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den_pipe = Signal() # Add a register to ease timing closure of den.
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self.comb += [
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self.di.eq(self.drp_dat_w.storage),
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@ -47,8 +50,9 @@ class _XADC(Module, AutoCSR):
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)
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]
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# Xilinx 7-Series System Monitor -------------------------------------------------------------------
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class XADC(_XADC, AutoCSR):
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class S7SystemMonitor(SystemMonitorDRP, AutoCSR):
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dadr_size = 7
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def __init__(self, analog_pads=None):
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@ -79,7 +83,7 @@ class XADC(_XADC, AutoCSR):
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eoc = Signal()
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eos = Signal()
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# XADC instance ----------------------------------------------------------------------------
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# XADC instance.
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self.dwe = Signal()
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self.den = Signal()
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self.drdy = Signal()
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@ -88,7 +92,7 @@ class XADC(_XADC, AutoCSR):
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self.do = Signal(16)
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self.drp_en = Signal()
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self.specials += Instance("XADC",
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# From ug480
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# From UG480
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p_INIT_40=0x9000, p_INIT_41=0x2ef0, p_INIT_42=0x0400,
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p_INIT_48=0x4701, p_INIT_49=0x000f,
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p_INIT_4A=0x4700, p_INIT_4B=0x0000,
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@ -127,12 +131,12 @@ class XADC(_XADC, AutoCSR):
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)
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]
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# Channels update --------------------------------------------------------------------------
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# Channels update.
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channels = {
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0: self.temperature,
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1: self.vccint,
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2: self.vccaux,
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6: self.vccbram
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0x0 : self.temperature,
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0x1 : self.vccint,
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0x2 : self.vccaux,
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0x6 : self.vccbram
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}
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self.sync += [
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If(self.drdy,
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@ -142,14 +146,17 @@ class XADC(_XADC, AutoCSR):
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)
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]
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# End of Convertion/Sequence update --------------------------------------------------------
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# End of Convertion/Sequence update.
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self.sync += [
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self.eoc.status.eq((self.eoc.status & ~self.eoc.we) | eoc),
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self.eos.status.eq((self.eos.status & ~self.eos.we) | eos),
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]
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class XADC(S7SystemMonitor): pass
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class USSYSMON(_XADC, AutoCSR):
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# Xilinx Ultrascale System Monitor -----------------------------------------------------------------
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class USSystemMonitor(SystemMonitorDRP, AutoCSR):
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dadr_size = 8
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def __init__(self, analog_pads=None):
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@ -186,7 +193,7 @@ class USSYSMON(_XADC, AutoCSR):
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eoc = Signal()
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eos = Signal()
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# SYSMONE1 instance ----------------------------------------------------------------------------
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# SYSMONE1 instance ------------------------------------------------------------------------
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self.dwe = Signal()
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self.den = Signal()
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self.drdy = Signal()
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@ -195,7 +202,7 @@ class USSYSMON(_XADC, AutoCSR):
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self.do = Signal(16)
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self.drp_en = Signal()
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self.specials += Instance("SYSMONE1",
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# From ug580
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# From UG580
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p_INIT_40=0x9000, p_INIT_41=0x2fd0, p_INIT_42=0x1000,
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p_INIT_46=0x000f, p_INIT_48=0x4701, p_INIT_49=0x000f,
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p_INIT_47=0x000f, p_INIT_4A=0x47e0, p_INIT_4B=0x0000,
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@ -234,12 +241,12 @@ class USSYSMON(_XADC, AutoCSR):
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)
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]
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# Channels update --------------------------------------------------------------------------
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# Channels update.
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channels = {
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0: self.temperature,
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1: self.vccint,
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2: self.vccaux,
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6: self.vccbram,
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0x0 : self.temperature,
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0x1 : self.vccint,
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0x2 : self.vccaux,
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0x6 : self.vccbram,
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0xd : self.vccpsintlp,
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0xe : self.vccpsintfp,
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0xf : self.vccpsaux,
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@ -252,7 +259,7 @@ class USSYSMON(_XADC, AutoCSR):
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)
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]
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# End of Convertion/Sequence update --------------------------------------------------------
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# End of Convertion/Sequence update.
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self.sync += [
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self.eoc.status.eq((self.eoc.status & ~self.eoc.we) | eoc),
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self.eos.status.eq((self.eos.status & ~self.eos.we) | eos),
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