build: Remove openfpga build backend (Replaced by osfpga build backend).
OpenFPGA build backend was an experimental build backend for OpenFPGA/SOFA chips. OpenFPGA is now providing a new FOEDAG build framework abstracting things and providing a regular .tcl/.sdc based toolchain.
This commit is contained in:
Florent Kermarrec
parent
aaf03b3860
commit
04f6b17d03
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from litex.build.openfpga.platform import OpenFPGAPlatform
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#!/usr/bin/env python3
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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from migen import *
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from litex.build.generic_platform import Pins
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from litex.build.openfpga import OpenFPGAPlatform
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# export LITEX_ENV_OPENFPGA=/home/florent/dev/openfpga/OpenFPGA
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# export LITEX_ENV_OPENFPGA_SOFA=/home/florent/dev/openfpga/SOFA
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# Minimal Platform ---------------------------------------------------------------------------------
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_io = [
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("clk", 0, Pins(1)),
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("led", 0, Pins(1))
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]
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class Platform(OpenFPGAPlatform):
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def __init__(self):
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OpenFPGAPlatform.__init__(self, "FPGA1212_QLSOFA_HD", _io)
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# Minimal Design -----------------------------------------------------------------------------------
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platform = Platform()
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clk = platform.request("clk")
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led = platform.request("led")
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module = Module()
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module.clock_domains.cd_sys = ClockDomain("sys")
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module.comb += module.cd_sys.clk.eq(clk)
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counter = Signal(26)
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module.comb += led.eq(counter[25])
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module.sync += counter.eq(counter + 1)
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# Build --------------------------------------------------------------------------------------------
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platform.build(module, run=True)
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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# OpenFPGA Special Overrides ---------------------------------------------------------------------
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openfpga_special_overrides = {}
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import sys
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import subprocess
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from shutil import which
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from migen.fhdl.structure import _Fragment
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from litex.build.generic_platform import *
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from litex.build import tools
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from litex.build.openfpga import common
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# Check Setup --------------------------------------------------------------------------------------
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def _check_setup():
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if os.getenv("LITEX_ENV_OPENFPGA", False) == False:
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msg = "Unable to find OpenFPGA toolchain, please:\n"
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msg += "- Set LITEX_ENV_OPENFPGA environment variant to OpenFPGA's settings path.\n"
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raise OSError(msg)
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if os.getenv("LITEX_ENV_OPENFPGA_SOFA", False) == False:
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msg = "Unable to find OpenFPGA's SOFA project, please:\n"
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msg += "- Set LITEX_ENV_OPENFPGA_SOFA environment variant to OpenFPGA's SOFA settings path.\n"
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raise OSError(msg)
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# Task Config -------------------------------------------------------------------------------------
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def _build_task_conf(platform, sources, build_dir, build_name):
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# Get Environnment variables.
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openfpga_path = os.getenv("LITEX_ENV_OPENFPGA")
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openfpga_sofa_path = os.getenv("LITEX_ENV_OPENFPGA_SOFA")
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# Get PnR/Task directories from OPENFPGA/SOFA paths.
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pnr_path = os.path.join(openfpga_sofa_path, platform.device + "_PNR")
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task_path = os.path.join(pnr_path, platform.device + "_task")
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# Get Config file.
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task_conf = os.path.join(task_path, "config", "task_simulation.conf")
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# Helpers.
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def replace_openfpga_task_section(filename, section, contents):
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lines = []
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# Read file and replace section with contents.
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copy = True
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for line in open(filename, "r"):
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if not copy and line.startswith("["):
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copy = True
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if line.startswith(section):
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copy = False
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lines.append(section + "\n")
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for l in contents:
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lines.append(l + "\n")
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lines.append("\n")
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if copy:
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lines.append(line)
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# Save file to .orig.
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os.system(f"mv {filename} {filename}.orig")
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# Write file with replaced section.
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with open(filename, "w") as f:
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f.write("".join(lines))
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# Add sources.
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bench_sources = []
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for filename, language, library in sources:
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if language is None:
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continue
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if language not in ["verilog"]:
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raise ValueError("OpenFPGA flow only supports verilog")
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bench_sources.append(filename)
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replace_openfpga_task_section(task_conf, "[BENCHMARKS]", [f"bench0={' '.join(bench_sources)}"])
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# Set Top-Level.
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replace_openfpga_task_section(task_conf, "[SYNTHESIS_PARAM]", [f"bench0_top={build_name}"])
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def _run_task(device):
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# Get Environnment variables.
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openfpga_path = os.getenv("LITEX_ENV_OPENFPGA")
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openfpga_sofa_path = os.getenv("LITEX_ENV_OPENFPGA_SOFA")
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# Get PnR/Task directories from OPENFPGA/SOFA paths.
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pnr_path = os.path.join(openfpga_sofa_path, device + "_PNR")
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task_path = os.path.join(pnr_path, device + "_task")
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# Set OPENFPGA_PATH.
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os.environ["OPENFPGA_PATH"] = os.getenv("LITEX_ENV_OPENFPGA")
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# Run OpenFPGA flow.
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build_cmd = ["make", "-C", pnr_path, "clean", "runOpenFPGA"]
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if subprocess.call(build_cmd) != 0:
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raise OSError("Error occured during OpenFPGA's flow execution.")
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# Copy artifacts.
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os.system("rm -rf run001")
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os.system(f"cp -r {task_path}/run001 run001")
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# Display log. FIXME: Do it during build?
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os.system("cat run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/openfpgashell.log")
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# OpenFPGAToolchain --------------------------------------------------------------------------------
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class OpenFPGAToolchain:
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attr_translate = {}
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special_overrides = common.openfpga_special_overrides
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def __init__(self):
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self.clocks = dict()
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self.false_paths = set()
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def build(self, platform, fragment,
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build_dir = "build",
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build_name = "top",
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run = False,
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**kwargs):
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# Create Build Directory.
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os.makedirs(build_dir, exist_ok=True)
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cwd = os.getcwd()
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os.chdir(build_dir)
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# Finalize Design.
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if not isinstance(fragment, _Fragment):
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fragment = fragment.get_fragment()
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platform.finalize(fragment)
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# Generate Verilog.
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v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
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named_sc, named_pc = platform.resolve_signals(v_output.ns)
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top_file = build_name + ".v"
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v_output.write(top_file)
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platform.add_source(top_file)
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# Check Setup.
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_check_setup()
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# Generate Task Config.
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_build_task_conf(platform, platform.sources, build_dir, build_name)
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# Run Task.
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if run:
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_run_task(platform.device)
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os.chdir(cwd)
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return v_output.ns
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@ -1,28 +0,0 @@
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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from litex.build.generic_platform import GenericPlatform
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from litex.build.openfpga import common, openfpga
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# OpenFPGAPlatform -------------------------------------------------------------------------------
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class OpenFPGAPlatform(GenericPlatform):
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def __init__(self, device, *args, **kwargs):
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GenericPlatform.__init__(self, device, *args, **kwargs)
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self.toolchain = openfpga.OpenFPGAToolchain()
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def get_verilog(self, *args, special_overrides=dict(), **kwargs):
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so = dict(common.openfpga_special_overrides)
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so.update(special_overrides)
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return GenericPlatform.get_verilog(self, *args,
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special_overrides = so,
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attr_translate = self.toolchain.attr_translate,
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**kwargs)
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def build(self, *args, **kwargs):
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return self.toolchain.build(self, *args, **kwargs)
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