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integration/export: Cosmetic cleanups.

This commit is contained in:
Florent Kermarrec 2021-08-24 19:13:16 +02:00
parent 44b223a918
commit 05a614c7a2
1 changed files with 36 additions and 38 deletions
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64
litex/soc/integration/export.py
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@ -18,6 +18,8 @@
import os import os
import json import json
import time
import datetime
import inspect import inspect
from shutil import which from shutil import which
from sysconfig import get_platform from sysconfig import get_platform
@ -33,14 +35,10 @@ from litex.soc.doc.module import gather_submodules, ModuleNotDocumented, Documen
from litex.soc.doc.csr import DocumentedCSRRegion from litex.soc.doc.csr import DocumentedCSRRegion
from litex.soc.interconnect.csr import _CompoundCSR from litex.soc.interconnect.csr import _CompoundCSR
# for generating a timestamp in the description field, if none is otherwise given
import datetime
import time
# CPU files ---------------------------------------------------------------------------------------- # CPU files ----------------------------------------------------------------------------------------
def get_cpu_mak(cpu, compile_software): def get_cpu_mak(cpu, compile_software):
# select between clang and gcc # Select between CLANG and GCC.
clang = os.getenv("CLANG", "") clang = os.getenv("CLANG", "")
if clang != "": if clang != "":
clang = bool(int(clang)) clang = bool(int(clang))
@ -48,11 +46,11 @@ def get_cpu_mak(cpu, compile_software):
clang = None clang = None
if cpu.clang_triple is None: if cpu.clang_triple is None:
if clang: if clang:
raise ValueError(cpu.name + " is not supported with clang.") raise ValueError(cpu.name + " is not supported with CLANG.")
else: else:
clang = False clang = False
else: else:
# Default to gcc unless told otherwise # Default to gcc unless told otherwise.
if clang is None: if clang is None:
clang = False clang = False
assert isinstance(clang, bool) assert isinstance(clang, bool)
@ -63,7 +61,7 @@ def get_cpu_mak(cpu, compile_software):
triple = cpu.gcc_triple triple = cpu.gcc_triple
flags = cpu.gcc_flags flags = cpu.gcc_flags
# select triple when more than one # Select triple when more than one.
def select_triple(triple): def select_triple(triple):
r = None r = None
if not isinstance(triple, tuple): if not isinstance(triple, tuple):
@ -74,7 +72,7 @@ def get_cpu_mak(cpu, compile_software):
p = get_platform() p = get_platform()
for i in range(len(triple)): for i in range(len(triple)):
t = triple[i] t = triple[i]
# use native toolchain if host and target platforms are the same # Use native toolchain if host and target platforms are the same.
if t == 'riscv64-unknown-elf' and p == 'linux-riscv64': if t == 'riscv64-unknown-elf' and p == 'linux-riscv64':
r = '--native--' r = '--native--'
break break
@ -90,7 +88,7 @@ def get_cpu_mak(cpu, compile_software):
raise OSError(msg) raise OSError(msg)
return r return r
# return informations # Return informations.
return [ return [
("TRIPLE", select_triple(triple)), ("TRIPLE", select_triple(triple)),
("CPU", cpu.name), ("CPU", cpu.name),
@ -102,13 +100,13 @@ def get_cpu_mak(cpu, compile_software):
def get_linker_output_format(cpu): def get_linker_output_format(cpu):
return "OUTPUT_FORMAT(\"" + cpu.linker_output_format + "\")\n" return f"OUTPUT_FORMAT(\"{cpu.linker_output_format}\")\n"
def get_linker_regions(regions): def get_linker_regions(regions):
r = "MEMORY {\n" r = "MEMORY {\n"
for name, region in regions.items(): for name, region in regions.items():
r += "\t{} : ORIGIN = 0x{:08x}, LENGTH = 0x{:08x}\n".format(name, region.origin, region.length) r += f"\t{name} : ORIGIN = 0x{region.origin:08x}, LENGTH = 0x{region.length:08x}\n"
r += "}\n" r += "}\n"
return r return r
@ -119,8 +117,8 @@ def get_git_header():
from litex.build.tools import get_migen_git_revision, get_litex_git_revision from litex.build.tools import get_migen_git_revision, get_litex_git_revision
r = generated_banner("//") r = generated_banner("//")
r += "#ifndef __GENERATED_GIT_H\n#define __GENERATED_GIT_H\n\n" r += "#ifndef __GENERATED_GIT_H\n#define __GENERATED_GIT_H\n\n"
r += "#define MIGEN_GIT_SHA1 \"{}\"\n".format(get_migen_git_revision()) r += f"#define MIGEN_GIT_SHA1 \"{get_migen_git_revision()}\"\n"
r += "#define LITEX_GIT_SHA1 \"{}\"\n".format(get_litex_git_revision()) r += f"#define LITEX_GIT_SHA1 \"{get_litex_git_revision()}\"\n"
r += "#endif\n" r += "#endif\n"
return r return r
@ -128,9 +126,9 @@ def get_mem_header(regions):
r = generated_banner("//") r = generated_banner("//")
r += "#ifndef __GENERATED_MEM_H\n#define __GENERATED_MEM_H\n\n" r += "#ifndef __GENERATED_MEM_H\n#define __GENERATED_MEM_H\n\n"
for name, region in regions.items(): for name, region in regions.items():
r += "#ifndef {name}_BASE\n".format(name=name.upper()) r += f"#ifndef {name.upper()}_BASE\n"
r += "#define {name}_BASE 0x{base:08x}L\n#define {name}_SIZE 0x{size:08x}\n".format( r += f"#define {name.upper()}_BASE 0x{region.origin:08x}L\n"
name=name.upper(), base=region.origin, size=region.length) r += f"#define {name.upper()}_SIZE 0x{region.length:08x}\n"
r += "#endif\n\n" r += "#endif\n\n"
r += "#ifndef MEM_REGIONS\n" r += "#ifndef MEM_REGIONS\n"
@ -175,14 +173,14 @@ def get_soc_header(constants, with_access_functions=True):
def _get_rw_functions_c(reg_name, reg_base, nwords, busword, alignment, read_only, with_access_functions): def _get_rw_functions_c(reg_name, reg_base, nwords, busword, alignment, read_only, with_access_functions):
r = "" r = ""
addr_str = "CSR_{}_ADDR".format(reg_name.upper()) addr_str = f"CSR_{reg_name.upper()}_ADDR"
size_str = "CSR_{}_SIZE".format(reg_name.upper()) size_str = f"CSR_{reg_name.upper()}_SIZE"
r += "#define {} (CSR_BASE + {}L)\n".format(addr_str, hex(reg_base)) r += f"#define {addr_str} (CSR_BASE + {hex(reg_base)}L)\n"
r += "#define {} {}\n".format(size_str, nwords) r += f"#define {size_str} {nwords}\n"
size = nwords*busword//8 size = nwords*busword//8
if size > 8: if size > 8:
# downstream should select appropriate `csr_[rd|wr]_buf_uintX()` pair! # Downstream should select appropriate `csr_[rd|wr]_buf_uintX()` pair!
return r return r
elif size > 4: elif size > 4:
ctype = "uint64_t" ctype = "uint64_t"
@ -195,25 +193,25 @@ def _get_rw_functions_c(reg_name, reg_base, nwords, busword, alignment, read_onl
stride = alignment//8; stride = alignment//8;
if with_access_functions: if with_access_functions:
r += "static inline {} {}_read(void) {{\n".format(ctype, reg_name) r += f"static inline {ctype} {reg_name}_read(void) {{\n"
if nwords > 1: if nwords > 1:
r += "\t{} r = csr_read_simple(CSR_BASE + {}L);\n".format(ctype, hex(reg_base)) r += f"\t{ctype} r = csr_read_simple(CSR_BASE + {reg_base}L);\n"
for sub in range(1, nwords): for sub in range(1, nwords):
r += "\tr <<= {};\n".format(busword) r += f"\tr <<= {busword};\n"
r += "\tr |= csr_read_simple(CSR_BASE + {}L);\n".format(hex(reg_base+sub*stride)) r += f"\tr |= csr_read_simple(CSR_BASE + {hex(reg_base+sub*stride)}L);\n"
r += "\treturn r;\n}\n" r += "\treturn r;\n}\n"
else: else:
r += "\treturn csr_read_simple(CSR_BASE + {}L);\n}}\n".format(hex(reg_base)) r += f"\treturn csr_read_simple(CSR_BASE + {hex(reg_base)}L);\n}}\n"
if not read_only: if not read_only:
r += "static inline void {}_write({} v) {{\n".format(reg_name, ctype) r += f"static inline void {reg_name}_write({ctype} v) {{\n"
for sub in range(nwords): for sub in range(nwords):
shift = (nwords-sub-1)*busword shift = (nwords-sub-1)*busword
if shift: if shift:
v_shift = "v >> {}".format(shift) v_shift = "v >> {}".format(shift)
else: else:
v_shift = "v" v_shift = "v"
r += "\tcsr_write_simple({}, CSR_BASE + {}L);\n".format(v_shift, hex(reg_base+sub*stride)) r += f"\tcsr_write_simple({v_shift}, CSR_BASE + {hex(reg_base+sub*stride)}L);\n"
r += "}\n" r += "}\n"
return r return r
@ -232,12 +230,12 @@ def get_csr_header(regions, constants, csr_base=None, with_access_functions=True
r += "#endif /* ! CSR_ACCESSORS_DEFINED */\n" r += "#endif /* ! CSR_ACCESSORS_DEFINED */\n"
csr_base = csr_base if csr_base is not None else regions[next(iter(regions))].origin csr_base = csr_base if csr_base is not None else regions[next(iter(regions))].origin
r += "#ifndef CSR_BASE\n" r += "#ifndef CSR_BASE\n"
r += "#define CSR_BASE {}L\n".format(hex(csr_base)) r += f"#define CSR_BASE {hex(csr_base)}L\n"
r += "#endif\n" r += "#endif\n"
for name, region in regions.items(): for name, region in regions.items():
origin = region.origin - csr_base origin = region.origin - csr_base
r += "\n/* "+name+" */\n" r += "\n/* "+name+" */\n"
r += "#define CSR_"+name.upper()+"_BASE (CSR_BASE + "+hex(origin)+"L)\n" r += f"#define CSR_{name.upper()}_BASE (CSR_BASE + {hex(origin)}L)\n"
if not isinstance(region.obj, Memory): if not isinstance(region.obj, Memory):
for csr in region.obj: for csr in region.obj:
nr = (csr.size + region.busword - 1)//region.busword nr = (csr.size + region.busword - 1)//region.busword
@ -248,8 +246,8 @@ def get_csr_header(regions, constants, csr_base=None, with_access_functions=True
for field in csr.fields.fields: for field in csr.fields.fields:
offset = str(field.offset) offset = str(field.offset)
size = str(field.size) size = str(field.size)
r += "#define CSR_"+name.upper()+"_"+csr.name.upper()+"_"+field.name.upper()+"_OFFSET "+offset+"\n" r += f"#define CSR_{name.upper()}_{csr.name.upper()}_{field.name.upper()}_OFFSET {offset}\n"
r += "#define CSR_"+name.upper()+"_"+csr.name.upper()+"_"+field.name.upper()+"_SIZE "+size+"\n" r += f"#define CSR_{name.upper()}_{csr.name.upper()}_{field.name.upper()}_SIZE {size}\n"
if with_access_functions and csr.size <= 32: # FIXME: Implement extract/read functions for csr.size > 32-bit. if with_access_functions and csr.size <= 32: # FIXME: Implement extract/read functions for csr.size > 32-bit.
reg_name = name + "_" + csr.name.lower() reg_name = name + "_" + csr.name.lower()
field_name = reg_name + "_" + field.name.lower() field_name = reg_name + "_" + field.name.lower()