integration/export: Cosmetic cleanups.
This commit is contained in:
Florent Kermarrec
parent
44b223a918
commit
05a614c7a2
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@ -18,6 +18,8 @@
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import os
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import json
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import time
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import datetime
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import inspect
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from shutil import which
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from sysconfig import get_platform
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@ -33,14 +35,10 @@ from litex.soc.doc.module import gather_submodules, ModuleNotDocumented, Documen
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from litex.soc.doc.csr import DocumentedCSRRegion
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from litex.soc.interconnect.csr import _CompoundCSR
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# for generating a timestamp in the description field, if none is otherwise given
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import datetime
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import time
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# CPU files ----------------------------------------------------------------------------------------
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def get_cpu_mak(cpu, compile_software):
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# select between clang and gcc
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# Select between CLANG and GCC.
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clang = os.getenv("CLANG", "")
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if clang != "":
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clang = bool(int(clang))
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@ -48,11 +46,11 @@ def get_cpu_mak(cpu, compile_software):
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clang = None
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if cpu.clang_triple is None:
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if clang:
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raise ValueError(cpu.name + " is not supported with clang.")
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raise ValueError(cpu.name + " is not supported with CLANG.")
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else:
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clang = False
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else:
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# Default to gcc unless told otherwise
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# Default to gcc unless told otherwise.
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if clang is None:
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clang = False
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assert isinstance(clang, bool)
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@ -63,7 +61,7 @@ def get_cpu_mak(cpu, compile_software):
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triple = cpu.gcc_triple
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flags = cpu.gcc_flags
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# select triple when more than one
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# Select triple when more than one.
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def select_triple(triple):
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r = None
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if not isinstance(triple, tuple):
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@ -74,7 +72,7 @@ def get_cpu_mak(cpu, compile_software):
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p = get_platform()
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for i in range(len(triple)):
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t = triple[i]
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# use native toolchain if host and target platforms are the same
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# Use native toolchain if host and target platforms are the same.
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if t == 'riscv64-unknown-elf' and p == 'linux-riscv64':
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r = '--native--'
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break
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@ -90,7 +88,7 @@ def get_cpu_mak(cpu, compile_software):
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raise OSError(msg)
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return r
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# return informations
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# Return informations.
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return [
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("TRIPLE", select_triple(triple)),
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("CPU", cpu.name),
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@ -102,13 +100,13 @@ def get_cpu_mak(cpu, compile_software):
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def get_linker_output_format(cpu):
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return "OUTPUT_FORMAT(\"" + cpu.linker_output_format + "\")\n"
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return f"OUTPUT_FORMAT(\"{cpu.linker_output_format}\")\n"
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def get_linker_regions(regions):
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r = "MEMORY {\n"
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for name, region in regions.items():
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r += "\t{} : ORIGIN = 0x{:08x}, LENGTH = 0x{:08x}\n".format(name, region.origin, region.length)
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r += f"\t{name} : ORIGIN = 0x{region.origin:08x}, LENGTH = 0x{region.length:08x}\n"
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r += "}\n"
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return r
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@ -119,8 +117,8 @@ def get_git_header():
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from litex.build.tools import get_migen_git_revision, get_litex_git_revision
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r = generated_banner("//")
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r += "#ifndef __GENERATED_GIT_H\n#define __GENERATED_GIT_H\n\n"
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r += "#define MIGEN_GIT_SHA1 \"{}\"\n".format(get_migen_git_revision())
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r += "#define LITEX_GIT_SHA1 \"{}\"\n".format(get_litex_git_revision())
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r += f"#define MIGEN_GIT_SHA1 \"{get_migen_git_revision()}\"\n"
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r += f"#define LITEX_GIT_SHA1 \"{get_litex_git_revision()}\"\n"
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r += "#endif\n"
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return r
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@ -128,9 +126,9 @@ def get_mem_header(regions):
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r = generated_banner("//")
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r += "#ifndef __GENERATED_MEM_H\n#define __GENERATED_MEM_H\n\n"
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for name, region in regions.items():
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r += "#ifndef {name}_BASE\n".format(name=name.upper())
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r += "#define {name}_BASE 0x{base:08x}L\n#define {name}_SIZE 0x{size:08x}\n".format(
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name=name.upper(), base=region.origin, size=region.length)
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r += f"#ifndef {name.upper()}_BASE\n"
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r += f"#define {name.upper()}_BASE 0x{region.origin:08x}L\n"
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r += f"#define {name.upper()}_SIZE 0x{region.length:08x}\n"
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r += "#endif\n\n"
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r += "#ifndef MEM_REGIONS\n"
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@ -175,14 +173,14 @@ def get_soc_header(constants, with_access_functions=True):
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def _get_rw_functions_c(reg_name, reg_base, nwords, busword, alignment, read_only, with_access_functions):
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r = ""
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addr_str = "CSR_{}_ADDR".format(reg_name.upper())
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size_str = "CSR_{}_SIZE".format(reg_name.upper())
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r += "#define {} (CSR_BASE + {}L)\n".format(addr_str, hex(reg_base))
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r += "#define {} {}\n".format(size_str, nwords)
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addr_str = f"CSR_{reg_name.upper()}_ADDR"
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size_str = f"CSR_{reg_name.upper()}_SIZE"
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r += f"#define {addr_str} (CSR_BASE + {hex(reg_base)}L)\n"
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r += f"#define {size_str} {nwords}\n"
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size = nwords*busword//8
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if size > 8:
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# downstream should select appropriate `csr_[rd|wr]_buf_uintX()` pair!
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# Downstream should select appropriate `csr_[rd|wr]_buf_uintX()` pair!
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return r
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elif size > 4:
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ctype = "uint64_t"
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@ -195,25 +193,25 @@ def _get_rw_functions_c(reg_name, reg_base, nwords, busword, alignment, read_onl
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stride = alignment//8;
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if with_access_functions:
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r += "static inline {} {}_read(void) {{\n".format(ctype, reg_name)
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r += f"static inline {ctype} {reg_name}_read(void) {{\n"
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if nwords > 1:
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r += "\t{} r = csr_read_simple(CSR_BASE + {}L);\n".format(ctype, hex(reg_base))
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r += f"\t{ctype} r = csr_read_simple(CSR_BASE + {reg_base}L);\n"
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for sub in range(1, nwords):
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r += "\tr <<= {};\n".format(busword)
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r += "\tr |= csr_read_simple(CSR_BASE + {}L);\n".format(hex(reg_base+sub*stride))
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r += f"\tr <<= {busword};\n"
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r += f"\tr |= csr_read_simple(CSR_BASE + {hex(reg_base+sub*stride)}L);\n"
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r += "\treturn r;\n}\n"
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else:
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r += "\treturn csr_read_simple(CSR_BASE + {}L);\n}}\n".format(hex(reg_base))
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r += f"\treturn csr_read_simple(CSR_BASE + {hex(reg_base)}L);\n}}\n"
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if not read_only:
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r += "static inline void {}_write({} v) {{\n".format(reg_name, ctype)
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r += f"static inline void {reg_name}_write({ctype} v) {{\n"
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for sub in range(nwords):
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shift = (nwords-sub-1)*busword
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if shift:
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v_shift = "v >> {}".format(shift)
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else:
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v_shift = "v"
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r += "\tcsr_write_simple({}, CSR_BASE + {}L);\n".format(v_shift, hex(reg_base+sub*stride))
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r += f"\tcsr_write_simple({v_shift}, CSR_BASE + {hex(reg_base+sub*stride)}L);\n"
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r += "}\n"
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return r
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@ -232,12 +230,12 @@ def get_csr_header(regions, constants, csr_base=None, with_access_functions=True
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r += "#endif /* ! CSR_ACCESSORS_DEFINED */\n"
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csr_base = csr_base if csr_base is not None else regions[next(iter(regions))].origin
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r += "#ifndef CSR_BASE\n"
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r += "#define CSR_BASE {}L\n".format(hex(csr_base))
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r += f"#define CSR_BASE {hex(csr_base)}L\n"
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r += "#endif\n"
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for name, region in regions.items():
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origin = region.origin - csr_base
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r += "\n/* "+name+" */\n"
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r += "#define CSR_"+name.upper()+"_BASE (CSR_BASE + "+hex(origin)+"L)\n"
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r += f"#define CSR_{name.upper()}_BASE (CSR_BASE + {hex(origin)}L)\n"
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if not isinstance(region.obj, Memory):
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for csr in region.obj:
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nr = (csr.size + region.busword - 1)//region.busword
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@ -248,8 +246,8 @@ def get_csr_header(regions, constants, csr_base=None, with_access_functions=True
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for field in csr.fields.fields:
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offset = str(field.offset)
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size = str(field.size)
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r += "#define CSR_"+name.upper()+"_"+csr.name.upper()+"_"+field.name.upper()+"_OFFSET "+offset+"\n"
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r += "#define CSR_"+name.upper()+"_"+csr.name.upper()+"_"+field.name.upper()+"_SIZE "+size+"\n"
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r += f"#define CSR_{name.upper()}_{csr.name.upper()}_{field.name.upper()}_OFFSET {offset}\n"
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r += f"#define CSR_{name.upper()}_{csr.name.upper()}_{field.name.upper()}_SIZE {size}\n"
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if with_access_functions and csr.size <= 32: # FIXME: Implement extract/read functions for csr.size > 32-bit.
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reg_name = name + "_" + csr.name.lower()
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field_name = reg_name + "_" + field.name.lower()
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