interconnect: For now remove the address_width checks; more verification will have to be done before enabling it to avoid regressions.

litex/soc/interconnect/axi/axi_full.py

@@ -554,19 +554,15 @@ class AXIDecoder(Module):
 # AXI Interconnect ---------------------------------------------------------------------------------
 
 def get_check_parameters(ports):
+    # FIXME: Add adr_width check.
+
     # Data-Width.
     data_width = ports[0].data_width
     if len(ports) > 1:
         for port in ports[1:]:
             assert port.data_width == data_width
 
-    # Address-Width.
-    address_width = ports[0].address_width
-    if len(ports) > 1:
-        for port in ports[1:]:
-            assert port.address_width == address_width
-
-    return data_width, address_width
+    return data_width
 
 class AXIInterconnectPointToPoint(Module):
     """AXI point to point interconnect"""
@@ -576,8 +572,8 @@ class AXIInterconnectPointToPoint(Module):
 class AXIInterconnectShared(Module):
     """AXI shared interconnect"""
     def __init__(self, masters, slaves, register=False, timeout_cycles=1e6):
-        data_width, address_width = get_check_parameters(ports=masters + [s for _, s in slaves])
-        shared = AXIInterface(data_width=data_width, address_width=address_width)
+        data_width = get_check_parameters(ports=masters + [s for _, s in slaves])
+        shared = AXIInterface(data_width=data_width)
         self.submodules.arbiter = AXIArbiter(masters, shared)
         self.submodules.decoder = AXIDecoder(shared, slaves)
         if timeout_cycles is not None:
@@ -589,9 +585,9 @@ class AXICrossbar(Module):
     MxN crossbar for M masters and N slaves.
     """
     def __init__(self, masters, slaves, register=False, timeout_cycles=1e6):
-        data_width, address_width = get_check_parameters(ports=masters + [s for _, s in slaves])
+        data_width = get_check_parameters(ports=masters + [s for _, s in slaves])
         matches, busses = zip(*slaves)
-        access_m_s = [[AXIInterface(data_width=data_width, address_width=address_width) for j in slaves] for i in masters]  # a[master][slave]
+        access_m_s = [[AXIInterface(data_width=data_width) for j in slaves] for i in masters]  # a[master][slave]
         access_s_m = list(zip(*access_m_s))  # a[slave][master]
         # Decode each master into its access row.
         for slaves, master in zip(access_m_s, masters):

litex/soc/interconnect/axi/axi_lite.py

@@ -746,19 +746,15 @@ class AXILiteDecoder(Module):
 # AXI-Lite Interconnect ----------------------------------------------------------------------------
 
 def get_check_parameters(ports):
+    # FIXME: Add adr_width check.
+
     # Data-Width.
     data_width = ports[0].data_width
     if len(ports) > 1:
         for port in ports[1:]:
             assert port.data_width == data_width
 
-    # Address-Width.
-    address_width = ports[0].address_width
-    if len(ports) > 1:
-        for port in ports[1:]:
-            assert port.address_width == address_width
-
-    return data_width, address_width
+    return data_width
 
 class AXILiteInterconnectPointToPoint(Module):
     """AXI Lite point to point interconnect"""
@@ -768,8 +764,8 @@ class AXILiteInterconnectPointToPoint(Module):
 class AXILiteInterconnectShared(Module):
     """AXI Lite shared interconnect"""
     def __init__(self, masters, slaves, register=False, timeout_cycles=1e6):
-        data_width, address_width = get_check_parameters(ports=masters + [s for _, s in slaves])
-        shared = AXILiteInterface(data_width=data_width, address_width=address_width)
+        data_width = get_check_parameters(ports=masters + [s for _, s in slaves])
+        shared = AXILiteInterface(data_width=data_width)
         self.submodules.arbiter = AXILiteArbiter(masters, shared)
         self.submodules.decoder = AXILiteDecoder(shared, slaves)
         if timeout_cycles is not None:
@@ -781,9 +777,9 @@ class AXILiteCrossbar(Module):
     MxN crossbar for M masters and N slaves.
     """
     def __init__(self, masters, slaves, register=False, timeout_cycles=1e6):
-        data_width, address_width = get_check_parameters(ports=masters + [s for _, s in slaves])
+        data_width = get_check_parameters(ports=masters + [s for _, s in slaves])
         matches, busses = zip(*slaves)
-        access_m_s = [[AXILiteInterface(data_width, address_width=address_width) for j in slaves] for i in masters]  # a[master][slave]
+        access_m_s = [[AXILiteInterface(data_width=data_width) for j in slaves] for i in masters]  # a[master][slave]
         access_s_m = list(zip(*access_m_s))  # a[slave][master]
         # Decode each master into its access row.
         for slaves, master in zip(access_m_s, masters):

litex/soc/interconnect/wishbone.py

@@ -144,19 +144,15 @@ class Timeout(Module):
 # Wishbone Interconnect ----------------------------------------------------------------------------
 
 def get_check_parameters(ports):
+    # FIXME: Add adr_width check.
+
     # Data-Width.
     data_width = ports[0].data_width
     if len(ports) > 1:
         for port in ports[1:]:
             assert port.data_width == data_width
 
-    # Address-Width.
-    adr_width = ports[0].adr_width
-    if len(ports) > 1:
-        for port in ports[1:]:
-            assert port.adr_width == adr_width
-
-    return data_width, adr_width
+    return data_width
 
 class InterconnectPointToPoint(Module):
     def __init__(self, master, slave):
@@ -237,8 +233,8 @@ class Decoder(Module):
 
 class InterconnectShared(Module):
     def __init__(self, masters, slaves, register=False, timeout_cycles=1e6):
-        data_width, adr_width = get_check_parameters(ports=masters + [s for _, s in slaves])
-        shared = Interface(data_width=data_width, adr_width=adr_width)
+        data_width = get_check_parameters(ports=masters + [s for _, s in slaves])
+        shared = Interface(data_width=data_width)
         self.submodules.arbiter = Arbiter(masters, shared)
         self.submodules.decoder = Decoder(shared, slaves, register)
         if timeout_cycles is not None:
@@ -247,9 +243,9 @@ class InterconnectShared(Module):
 
 class Crossbar(Module):
     def __init__(self, masters, slaves, register=False, timeout_cycles=1e6):
-        data_width, adr_width = get_check_parameters(ports=masters + [s for _, s in slaves])
+        data_width = get_check_parameters(ports=masters + [s for _, s in slaves])
         matches, busses = zip(*slaves)
-        access = [[Interface(data_width=data_width, adr_width=adr_width) for j in slaves] for i in masters]
+        access = [[Interface(data_width=data_width) for j in slaves] for i in masters]
         # decode each master into its access row
         for row, master in zip(access, masters):
             row = list(zip(matches, row))