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soc/interconnect/wishbone: increase bus error timeout to 1e6 cycles

This commit is contained in:
Florent Kermarrec 2019-01-27 08:23:44 +01:00
parent 02708d3b0f
commit 05dcb5cadc
1 changed files with 2 additions and 2 deletions
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4
litex/soc/interconnect/wishbone.py
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@ -140,7 +140,7 @@ class Timeout(Module):
# # # # # #
timer = WaitTimer(cycles) timer = WaitTimer(int(cycles))
self.submodules += timer self.submodules += timer
self.comb += [ self.comb += [
timer.wait.eq(master.stb & master.cyc & ~master.ack), timer.wait.eq(master.stb & master.cyc & ~master.ack),
@ -153,7 +153,7 @@ class Timeout(Module):
class InterconnectShared(Module): class InterconnectShared(Module):
def __init__(self, masters, slaves, register=False, timeout_cycles=2**16): def __init__(self, masters, slaves, register=False, timeout_cycles=1e6):
shared = Interface() shared = Interface()
self.submodules.arbiter = Arbiter(masters, shared) self.submodules.arbiter = Arbiter(masters, shared)
self.submodules.decoder = Decoder(shared, slaves, register) self.submodules.decoder = Decoder(shared, slaves, register)