soc/init_ram: Define and use contents_size.
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@ -1069,11 +1069,12 @@ class SoC(LiteXModule, SoCCoreCompat):
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True : "ROM",
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True : "ROM",
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False : "RAM",
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False : "RAM",
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}["w" not in ram_region.mode]
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}["w" not in ram_region.mode]
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contents_size = 4*len(contents) # FIXME.
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# Size Check.
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# Size Check.
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if ram_region.size < 4*len(contents):
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if ram_region.size < contents_size:
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self.logger.error("Contents Size ({}) {} {} Size ({}).".format(
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self.logger.error("Contents Size ({}) {} {} Size ({}).".format(
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colorer(f"0x{4*len(contents):x}"),
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colorer(f"0x{contents_size:x}"),
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colorer("exceeds", color="red"),
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colorer("exceeds", color="red"),
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ram_type,
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ram_type,
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colorer(f"0x{ram_region.size:x}"),
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colorer(f"0x{ram_region.size:x}"),
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@ -1084,7 +1085,7 @@ class SoC(LiteXModule, SoCCoreCompat):
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self.logger.info("Initializing {} {} with contents (Size: {}).".format(
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self.logger.info("Initializing {} {} with contents (Size: {}).".format(
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ram_type,
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ram_type,
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colorer(name),
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colorer(name),
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colorer(f"0x{4*len(contents):x}")))
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colorer(f"0x{contents_size:x}")))
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ram.mem.init = contents
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ram.mem.init = contents
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# RAM Auto-Resize (Optional).
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# RAM Auto-Resize (Optional).
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@ -1093,7 +1094,7 @@ class SoC(LiteXModule, SoCCoreCompat):
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ram_type,
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ram_type,
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colorer(name),
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colorer(name),
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colorer(f"0x{ram_region.size:x}"),
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colorer(f"0x{ram_region.size:x}"),
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colorer(f"0x{4*len(contents):x}")))
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colorer(f"0x{contents_size:x}")))
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ram.mem.depth = len(contents)
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ram.mem.depth = len(contents)
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def add_rom(self, name, origin, size, contents=[], mode="rx"):
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def add_rom(self, name, origin, size, contents=[], mode="rx"):
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