Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

sram: do not use MemoryPort

Browse source
This commit is contained in:
Sebastien Bourdeauducq 2012-11-26 19:32:56 +01:00
parent 0c29775a8f
commit 0620e75cb8
1 changed files with 11 additions and 9 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

20
milkymist/sram/__init__.py
View file

@ -7,14 +7,18 @@ class SRAM:
self.depth = depth self.depth = depth
def get_fragment(self): def get_fragment(self):
# memory
mem = Memory(32, self.depth)
port = mem.get_port(write_capable=True, we_granularity=8)
# generate write enable signal # generate write enable signal
we = Signal(BV(4)) comb = [port.we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
comb = [we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
for i in range(4)] for i in range(4)]
# split address # address and data
nbits = bits_for(self.depth-1) comb += [
partial_adr = Signal(BV(nbits)) port.adr.eq(self.bus.adr[:len(port.adr)]),
comb.append(partial_adr.eq(self.bus.adr[:nbits])) port.dat_w.eq(self.bus.dat_w),
self.bus.dat_r.eq(port.dat_r)
]
# generate ack # generate ack
sync = [ sync = [
self.bus.ack.eq(0), self.bus.ack.eq(0),
@ -22,6 +26,4 @@ class SRAM:
self.bus.ack.eq(1) self.bus.ack.eq(1)
) )
] ]
# memory return Fragment(comb, sync, memories=[mem])
port = MemoryPort(partial_adr, self.bus.dat_r, we, self.bus.dat_w, we_granularity=8)
return Fragment(comb, sync, memories=[Memory(32, self.depth, port)])