framebuffer: support df debugger
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@ -247,9 +247,10 @@ class Framebuffer:
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"hres", "hsync_start", "hsync_end", "hscan",
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"vres", "vsync_start", "vsync_end", "vscan"])
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g.add_connection(vtg, fifo)
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self._comp_actor = CompositeActor(g)
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self._comp_actor = CompositeActor(g, debugger=False)
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self.bank = csrgen.Bank(fi.actor.get_registers(), address=address)
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self.bank = csrgen.Bank(fi.actor.get_registers() + self._comp_actor.get_registers(),
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address=address)
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# VGA clock input
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if not simulation:
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