Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

soc_core: set csr to 0x00000000 when there is no wishbone

Browse source
This commit is contained in:
Florent Kermarrec 2019-09-23 15:57:14 +02:00
parent ad8830d977
commit 06d0806494
1 changed files with 3 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
litex/soc/integration/soc_core.py
View file

@ -205,6 +205,9 @@ class SoCCore(Module):
if cpu_type == "None":
cpu_type = None
if not with_wishbone:
self.soc_mem_map["csr"] = 0x00000000
self.cpu_type = cpu_type
self.cpu_variant = cpu.check_format_cpu_variant(cpu_variant)