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soc_core: set csr to 0x00000000 when there is no wishbone

This commit is contained in:
Florent Kermarrec 2019-09-23 15:57:14 +02:00
parent ad8830d977
commit 06d0806494
1 changed files with 3 additions and 0 deletions
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3
litex/soc/integration/soc_core.py
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@ -205,6 +205,9 @@ class SoCCore(Module):
if cpu_type == "None": if cpu_type == "None":
cpu_type = None cpu_type = None
if not with_wishbone:
self.soc_mem_map["csr"] = 0x00000000
self.cpu_type = cpu_type self.cpu_type = cpu_type
self.cpu_variant = cpu.check_format_cpu_variant(cpu_variant) self.cpu_variant = cpu.check_format_cpu_variant(cpu_variant)