Fix Wishbone arbiter
Right now, when multiple masters want to access the bus, access is granted to one of them, and is not revoked until selected master has finished all of its transactions (cyc goes low). This state causes master starvation if access is granted to high bandwidth master, like cpu in busy loop. This commit makes it so access to bus is revoked when pending transaction is finished (ack and cyc are high) or when selected master is idle. Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
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@ -166,7 +166,8 @@ class Arbiter(Module):
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if controllers is not None:
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if controllers is not None:
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masters = controllers
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masters = controllers
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self.submodules.rr = roundrobin.RoundRobin(len(masters))
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self.submodules.rr = roundrobin.RoundRobin(len(masters), roundrobin.SP_CE)
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cycs = Array(m.cyc for m in masters)
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# mux master->slave signals
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# mux master->slave signals
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for name, size, direction in _layout:
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for name, size, direction in _layout:
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@ -185,6 +186,8 @@ class Arbiter(Module):
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else:
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else:
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self.comb += dest.eq(source)
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self.comb += dest.eq(source)
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self.comb += self.rr.ce.eq(target.ack | ~cycs[self.rr.grant])
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# connect bus requests to round-robin selector
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# connect bus requests to round-robin selector
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reqs = [m.cyc for m in masters]
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reqs = [m.cyc for m in masters]
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self.comb += self.rr.request.eq(Cat(*reqs))
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self.comb += self.rr.request.eq(Cat(*reqs))
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