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ulx3s: Connect SDRAM clock

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2018-10-31 13:29:35 +00:00
parent 8404434956
commit 0729b3a059
1 changed files with 2 additions and 0 deletions
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2
litex/boards/targets/ulx3s.py
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@ -45,6 +45,8 @@ class _CRG(Module):
o_Z=new_sdram_ps_clk)
sdram_ps_clk = new_sdram_ps_clk
self.comb += self.cd_sys_ps.clk.eq(sdram_ps_clk)
sdram_clock = platform.request("sdram_clock")
self.comb += sdram_clock.eq(sdram_ps_clk)
# Stop ESP32 from resetting FPGA
wifi_gpio0 = platform.request("wifi_gpio0")