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cpu/vexriscv_smp: Add specialization of the RAM implementation based on the FPGA family (Platform). 

RAMXilinx was not infered correctly on Intel/Altera devices, we now have an Intel/Altera specific
implementation and could add other specific implementations in the future if required.
This commit is contained in:
Florent Kermarrec 2021-03-30 11:10:05 +02:00
parent 70d11974fc
commit 080ecad522
1 changed files with 12 additions and 1 deletions
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13
litex/soc/cores/cpu/vexriscv_smp/core.py
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@ -331,7 +331,18 @@ class VexRiscvSMP(CPU):
if not path.exists(os.path.join(vdir, self.cluster_name + ".v")): if not path.exists(os.path.join(vdir, self.cluster_name + ".v")):
self.generate_netlist() self.generate_netlist()
platform.add_source(os.path.join(vdir, "RamXilinx.v"), "verilog")
# Add RAM.
# By default, use Generic RAM implementation.
ram_filename = "Ram_1w_1rs_Generic.v"
# On Altera/Intel platforms, use specific implementation.
from litex.build.altera import AlteraPlatform
if isinstance(platform, AlteraPlatform):
ram_filename = "Ram_1w_1rs_Intel.v"
platform.add_source(os.path.join(vdir, ram_filename), "verilog")
# Add Cluster.
platform.add_source(os.path.join(vdir, self.cluster_name + ".v"), "verilog") platform.add_source(os.path.join(vdir, self.cluster_name + ".v"), "verilog")
def add_soc_components(self, soc, soc_region_cls): def add_soc_components(self, soc, soc_region_cls):