targets: use new clock abstraction on all 7-series targets
This commit is contained in:
Florent Kermarrec
parent
74e74dc0e7
commit
082b03016c
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@ -3,10 +3,10 @@
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.boards.platforms import genesys2
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import mem_decoder
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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@ -19,59 +19,19 @@ from liteeth.core.mac import LiteEthMAC
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class _CRG(Module):
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def __init__(self, platform):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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clk200 = platform.request("clk200")
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clk200_se = Signal()
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self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se)
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self.submodules.pll = pll = S7MMCM()
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self.comb += pll.reset.eq(~platform.request("cpu_reset_n"))
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pll.register_clkin(platform.request("clk200"), 200e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_clk200, 200e6)
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rst_n = platform.request("cpu_reset_n")
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pll_locked = Signal()
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pll_fb = Signal()
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pll_sys = Signal()
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pll_sys4x = Signal()
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pll_clk200 = Signal()
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self.specials += [
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Instance("PLLE2_BASE",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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# VCO @ 1GHz
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
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p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
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i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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# 125MHz
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p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=pll_sys,
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# 500MHz
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p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0,
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o_CLKOUT1=pll_sys4x,
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# 200MHz
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p_CLKOUT2_DIVIDE=5, p_CLKOUT2_PHASE=0.0,
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o_CLKOUT2=pll_clk200
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),
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Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
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Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
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Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll_locked | ~rst_n),
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AsyncResetSynchronizer(self.cd_clk200, ~pll_locked | ~rst_n),
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]
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reset_counter = Signal(4, reset=15)
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ic_reset = Signal(reset=1)
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self.sync.clk200 += \
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If(reset_counter != 0,
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reset_counter.eq(reset_counter - 1)
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).Else(
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ic_reset.eq(0)
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)
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self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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class BaseSoC(SoCSDRAM):
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@ -87,7 +47,7 @@ class BaseSoC(SoCSDRAM):
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integrated_sram_size=0x8000,
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**kwargs)
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self.submodules.crg = _CRG(platform)
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# sdram
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self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
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@ -3,10 +3,10 @@
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.boards.platforms import kc705
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import mem_decoder
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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@ -19,59 +19,19 @@ from liteeth.core.mac import LiteEthMAC
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class _CRG(Module):
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def __init__(self, platform):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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clk200 = platform.request("clk200")
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clk200_se = Signal()
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self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se)
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self.submodules.pll = pll = S7MMCM()
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self.comb += pll.reset.eq(platform.request("cpu_reset"))
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pll.register_clkin(platform.request("clk200"), 200e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_clk200, 200e6)
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rst = platform.request("cpu_reset")
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pll_locked = Signal()
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pll_fb = Signal()
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pll_sys = Signal()
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pll_sys4x = Signal()
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pll_clk200 = Signal()
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self.specials += [
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Instance("PLLE2_BASE",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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# VCO @ 1GHz
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
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p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
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i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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# 125MHz
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p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=pll_sys,
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# 500MHz
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p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0,
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o_CLKOUT1=pll_sys4x,
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# 200MHz
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p_CLKOUT2_DIVIDE=5, p_CLKOUT2_PHASE=0.0,
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o_CLKOUT2=pll_clk200
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),
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Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
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Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
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Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll_locked | rst),
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AsyncResetSynchronizer(self.cd_clk200, ~pll_locked | rst),
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]
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reset_counter = Signal(4, reset=15)
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ic_reset = Signal(reset=1)
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self.sync.clk200 += \
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If(reset_counter != 0,
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reset_counter.eq(reset_counter - 1)
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).Else(
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ic_reset.eq(0)
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)
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self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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class BaseSoC(SoCSDRAM):
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@ -87,7 +47,7 @@ class BaseSoC(SoCSDRAM):
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integrated_sram_size=0x8000,
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**kwargs)
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self.submodules.crg = _CRG(platform)
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# sdram
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self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
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@ -3,10 +3,10 @@
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.boards.platforms import nexys4ddr
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import mem_decoder
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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@ -16,66 +16,23 @@ from litedram.phy import s7ddrphy
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class _CRG(Module):
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def __init__(self, platform):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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self.clock_domains.cd_clk100 = ClockDomain()
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clk100 = platform.request("clk100")
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rst = ~platform.request("cpu_reset")
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self.submodules.pll = pll = S7MMCM()
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self.comb += pll.reset.eq(~platform.request("cpu_reset"))
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pll.register_clkin(platform.request("clk100"), 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys2x_dqs, 2*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_clk200, 200e6)
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pll.create_clkout(self.cd_clk100, 100e6)
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pll_locked = Signal()
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pll_fb = Signal()
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pll_sys = Signal()
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pll_sys2x = Signal()
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pll_sys2x_dqs = Signal()
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pll_clk200 = Signal()
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self.specials += [
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Instance("PLLE2_BASE",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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# VCO @ 1600 MHz
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=10.0,
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p_CLKFBOUT_MULT=16, p_DIVCLK_DIVIDE=1,
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i_CLKIN1=clk100, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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# 100 MHz
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p_CLKOUT0_DIVIDE=16, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=pll_sys,
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# 200 MHz
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p_CLKOUT1_DIVIDE=8, p_CLKOUT1_PHASE=0.0,
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o_CLKOUT1=pll_sys2x,
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# 200 MHz dqs
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p_CLKOUT2_DIVIDE=8, p_CLKOUT2_PHASE=90.0,
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o_CLKOUT2=pll_sys2x_dqs,
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# 200 MHz
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p_CLKOUT3_DIVIDE=8, p_CLKOUT3_PHASE=0.0,
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o_CLKOUT3=pll_clk200
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),
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Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
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Instance("BUFG", i_I=pll_sys2x, o_O=self.cd_sys2x.clk),
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Instance("BUFG", i_I=pll_sys2x_dqs, o_O=self.cd_sys2x_dqs.clk),
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Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
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Instance("BUFG", i_I=clk100, o_O=self.cd_clk100.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll_locked | rst),
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AsyncResetSynchronizer(self.cd_clk200, ~pll_locked | rst),
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AsyncResetSynchronizer(self.cd_clk100, ~pll_locked | rst),
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]
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reset_counter = Signal(4, reset=15)
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ic_reset = Signal(reset=1)
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self.sync.clk200 += \
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If(reset_counter != 0,
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reset_counter.eq(reset_counter - 1)
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).Else(
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ic_reset.eq(0)
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)
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self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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class BaseSoC(SoCSDRAM):
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@ -91,7 +48,7 @@ class BaseSoC(SoCSDRAM):
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integrated_sram_size=0x8000,
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**kwargs)
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self.submodules.crg = _CRG(platform)
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# sdram
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype="DDR2", nphases=2, sys_clk_freq=sys_clk_freq)
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@ -3,10 +3,10 @@
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.boards.platforms import nexys_video
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import mem_decoder
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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@ -19,66 +19,23 @@ from liteeth.core.mac import LiteEthMAC
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class _CRG(Module):
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def __init__(self, platform):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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self.clock_domains.cd_clk100 = ClockDomain()
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clk100 = platform.request("clk100")
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rst = ~platform.request("cpu_reset")
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self.submodules.pll = pll = S7MMCM()
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self.comb += pll.reset.eq(~platform.request("cpu_reset"))
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pll.register_clkin(platform.request("clk100"), 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_clk200, 200e6)
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pll.create_clkout(self.cd_clk100, 100e6)
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pll_locked = Signal()
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pll_fb = Signal()
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pll_sys = Signal()
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pll_sys4x = Signal()
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pll_sys4x_dqs = Signal()
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pll_clk200 = Signal()
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self.specials += [
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Instance("PLLE2_BASE",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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# VCO @ 1600 MHz
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=10.0,
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p_CLKFBOUT_MULT=16, p_DIVCLK_DIVIDE=1,
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i_CLKIN1=clk100, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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# 100 MHz
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p_CLKOUT0_DIVIDE=16, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=pll_sys,
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# 400 MHz
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p_CLKOUT1_DIVIDE=4, p_CLKOUT1_PHASE=0.0,
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o_CLKOUT1=pll_sys4x,
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# 400 MHz dqs
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p_CLKOUT2_DIVIDE=4, p_CLKOUT2_PHASE=90.0,
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o_CLKOUT2=pll_sys4x_dqs,
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# 200 MHz
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p_CLKOUT3_DIVIDE=8, p_CLKOUT3_PHASE=0.0,
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o_CLKOUT3=pll_clk200
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),
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Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
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Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
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Instance("BUFG", i_I=pll_sys4x_dqs, o_O=self.cd_sys4x_dqs.clk),
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Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
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Instance("BUFG", i_I=clk100, o_O=self.cd_clk100.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll_locked | rst),
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AsyncResetSynchronizer(self.cd_clk200, ~pll_locked | rst),
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AsyncResetSynchronizer(self.cd_clk100, ~pll_locked | rst),
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]
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reset_counter = Signal(4, reset=15)
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ic_reset = Signal(reset=1)
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self.sync.clk200 += \
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If(reset_counter != 0,
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reset_counter.eq(reset_counter - 1)
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).Else(
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ic_reset.eq(0)
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)
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self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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class BaseSoC(SoCSDRAM):
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@ -94,7 +51,7 @@ class BaseSoC(SoCSDRAM):
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integrated_sram_size=0x8000,
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**kwargs)
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self.submodules.crg = _CRG(platform)
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# sdram
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
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