Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Do not specify period constraints twice

This commit is contained in:
Sebastien Bourdeauducq 2013-07-04 19:25:29 +02:00
parent 0784cd164f
commit 0883e99de3
3 changed files with 6 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
mibuild/platforms/m1.py
View File

@ -119,7 +119,7 @@ _io = [
class Platform(XilinxISEPlatform):
def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io,
lambda p: CRG_SE(p, "clk50", "user_btn", 20.0))
lambda p: CRG_SE(p, "clk50", "user_btn"))
def do_finalize(self, fragment):
try:

2
mibuild/platforms/mixxeo.py
View File

@ -143,7 +143,7 @@ _io = [
class Platform(XilinxISEPlatform):
def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-3", _io,
lambda p: CRG_SE(p, "clk50", None, 20.0))
lambda p: CRG_SE(p, "clk50", None))
self.add_platform_command("CONFIG VCCAUX=\"3.3\";\n")
def do_finalize(self, fragment):

7
mibuild/xilinx_ise.py
View File

@ -10,16 +10,17 @@ from mibuild.crg import SimpleCRG
from mibuild import tools
def _add_period_constraint(platform, clk, period):
platform.add_platform_command("""NET "{clk}" TNM_NET = "GRPclk";
if period is not None:
platform.add_platform_command("""NET "{clk}" TNM_NET = "GRPclk";
TIMESPEC "TSclk" = PERIOD "GRPclk" """+str(period)+""" ns HIGH 50%;""", clk=clk)
class CRG_SE(SimpleCRG):
def __init__(self, platform, clk_name, rst_name, period, rst_invert=False):
def __init__(self, platform, clk_name, rst_name, period=None, rst_invert=False):
SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert)
_add_period_constraint(platform, self._clk, period)
class CRG_DS(Module):
def __init__(self, platform, clk_name, rst_name, period, rst_invert=False):
def __init__(self, platform, clk_name, rst_name, period=None, rst_invert=False):
reset_less = rst_name is None
self.clock_domains.cd_sys = ClockDomain(reset_less=reset_less)
self._clk = platform.request(clk_name)