build/generic_toolchain: Fix build/copyrights and do minor cosmetic changes.

litex/build/altera/quartus.py

@@ -4,6 +4,7 @@
 # Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
 # Copyright (c) 2019 msloniewski <marcin.sloniewski@gmail.com>
 # Copyright (c) 2019 vytautasb <v.buitvydas@limemicro.com>
+# Copyright (c) 2022 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
 # SPDX-License-Identifier: BSD-2-Clause
 
 import os
@@ -168,8 +169,6 @@ class AlteraQuartusToolchain(GenericToolchain):
     def build_script(self):
         build_name = self._build_name
 
-        self._build_qsf()
-
         if sys.platform in ["win32", "cygwin"]:
             script_file = "build_" + build_name + ".bat"
             script_contents = "REM Autogenerated by LiteX / git: " + tools.get_litex_git_revision() + "\n"

litex/build/generic_toolchain.py

@@ -1,24 +1,15 @@
 #
 # This file is part of LiteX.
 #
-# Copyright (c) 2017-2018 William D. Jones <thor0505@comcast.net>
-# Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
+# Copyright (c) 2012-2022 Florent Kermarrec <florent@enjoy-digital.fr>
 # Copyright (c) 2022 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
 # SPDX-License-Identifier: BSD-2-Clause
 
-
 import os
-import sys
-import subprocess
-from shutil import which
 
 from migen.fhdl.structure import _Fragment
 
-from litex.build.generic_platform import *
-from litex.build import tools
-
-
-# GenericToolchain -------------------------------------------------------------------------
+# Generic Toolchain --------------------------------------------------------------------------------
 
 class GenericToolchain:
     attr_translate = {
@@ -26,18 +17,22 @@ class GenericToolchain:
     }
 
     def __init__(self):
-        self.clocks    = dict()
+        self.clocks      = dict()
         self.false_paths = set() # FIXME: use it
-        self.named_pc = []
-        self.named_sc = []
+        self.named_pc    = []
+        self.named_sc    = []
 
-    # method use to build timing params
-    def build_timing_constr(self, vns, clocks):
-        pass
+    def build_constr_file(self, named_sc, named_pc):
+        raise NotImplementedError("GenericToolchain.build_constr_file must be overloaded.")
 
-    # method use to build project (if required)
     def build_timing_constr(self, vns, clocks):
-        pass
+        pass # Pass since optional.
+
+    def build_project(self):
+        pass # Pass since optional.
+
+    def build_script(self):
+        raise NotImplementedError("GenericToolchain.build_script must be overloaded.")
 
     def _build(self, platform, fragment,
         build_dir      = "build",
@@ -50,36 +45,36 @@ class GenericToolchain:
         self._synth_opts = synth_opts
         self.platform    = platform
 
-        # Create build directory
+        # Create Build Directory.
         os.makedirs(build_dir, exist_ok=True)
         cwd = os.getcwd()
         os.chdir(build_dir)
 
-        # Finalize design
+        # Finalize Design.
         if not isinstance(fragment, _Fragment):
             fragment = fragment.get_fragment()
         platform.finalize(fragment)
 
-        # Generate verilog
+        # Generate Verilog.
         v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
         self.named_sc, self.named_pc = platform.resolve_signals(v_output.ns)
         v_file = build_name + ".v"
         v_output.write(v_file)
         platform.add_source(v_file)
 
-        # Generate design io constraints file
+        # Generate Design IO Constraints File.
         self.build_constr_file(self.named_sc, self.named_pc)
 
-        # Generate design timing constraints file (in timing_constr file)
+        # Generate Design Timing Constraints File.
         self.build_timing_constr(v_output.ns, self.clocks)
 
-        # Generate project
+        # Generate project.
         self.build_project()
 
-        # Generate build script
+        # Generate build script.
         script = self.build_script()
 
-        # Run
+        # Run.
         if run:
             self.run_script(script)
 

litex/build/lattice/icestorm.py

@@ -3,6 +3,7 @@
 #
 # Copyright (c) 2017-2018 William D. Jones <thor0505@comcast.net>
 # Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
+# Copyright (c) 2022 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
 # SPDX-License-Identifier: BSD-2-Clause
 
 
@@ -56,7 +57,7 @@ class LatticeIceStormToolchain(GenericToolchain):
                 r += "set_io {} {}\n".format(sig, pins[0])
         if named_pc:
             r += "\n" + "\n\n".join(named_pc)
-        tools.write_to_file(self._build_name + "pcf", r)
+        tools.write_to_file(self._build_name + ".pcf", r)
 
     # Timing Constraints (in pre_pack file) ------------------------------------------------------------
 
@@ -81,7 +82,7 @@ class LatticeIceStormToolchain(GenericToolchain):
                 language, includes, filename))
         return "\n".join(reads)
 
-    # Project (ys) -------------------------------------------------------------------------------------
+    # Yosys/Nextpnr Helpers/Templates ------------------------------------------------------------------
 
     _yosys_template = [
         "verilog_defaults -push",
@@ -92,7 +93,7 @@ class LatticeIceStormToolchain(GenericToolchain):
         "synth_ice40 {synth_opts} -json {build_name}.json -top {build_name} -dsp",
     ]
 
-    def build_project(self):
+    def _build_yosys(self):
         ys = []
         for l in self._yosys_template:
             ys.append(l.format(
@@ -112,6 +113,8 @@ class LatticeIceStormToolchain(GenericToolchain):
     ]
 
     def build_script(self):
+        # Generate Yosys script
+        self._build_yosys()
         # Translate device to Nextpnr architecture/package
         (family, architecture, package) = self.parse_device()
 
@@ -140,7 +143,7 @@ class LatticeIceStormToolchain(GenericToolchain):
 
         return script_file
 
-    def run_script(script):
+    def run_script(self, script):
         if sys.platform in ("win32", "cygwin"):
             shell = ["cmd", "/c"]
         else:

litex/build/lattice/trellis.py

@@ -4,6 +4,7 @@
 # Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
 # Copyright (c) 2018-2019 David Shah <dave@ds0.me>
 # Copyright (c) 2018 William D. Jones <thor0505@comcast.net>
+# Copyright (c) 2022 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
 # SPDX-License-Identifier: BSD-2-Clause
 
 import os