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Refactor code

This commit is contained in:
Jiajie Chen 2023-04-20 19:00:26 +08:00
parent 4731aa6522
commit 0976c5aa54
1 changed files with 2 additions and 40 deletions
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42
litex/soc/software/liblitedram/sdram.c
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@ -565,26 +565,7 @@ int _sdram_write_leveling_cdly_range_end = -1;
static void sdram_write_leveling_on(void) { static void sdram_write_leveling_on(void) {
// Flip write leveling bit in the Mode Register, as it is disabled by default // Flip write leveling bit in the Mode Register, as it is disabled by default
#ifndef SDRAM_PHY_CLAM_SHELL sdram_mode_register_write(DDRX_MR_WRLVL_ADDRESS, DDRX_MR_WRLVL_RESET ^ (1 << DDRX_MR_WRLVL_BIT));
sdram_dfii_pi0_address_write(DDRX_MR_WRLVL_RESET ^ (1 << DDRX_MR_WRLVL_BIT));
sdram_dfii_pi0_baddress_write(DDRX_MR_WRLVL_ADDRESS);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
#else
sdram_dfii_pi0_address_write(DDRX_MR_WRLVL_RESET ^ (1 << DDRX_MR_WRLVL_BIT));
sdram_dfii_pi0_baddress_write(DDRX_MR_WRLVL_ADDRESS);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS_TOP);
int addr = DDRX_MR_WRLVL_RESET ^ (1 << DDRX_MR_WRLVL_BIT);
int baddr = DDRX_MR_WRLVL_ADDRESS;
addr = swap_bit(addr, 3, 4);
addr = swap_bit(addr, 5, 6);
addr = swap_bit(addr, 7, 8);
addr = swap_bit(addr, 11, 13);
baddr = swap_bit(baddr, 0, 1);
sdram_dfii_pi0_address_write(addr);
sdram_dfii_pi0_baddress_write(baddr);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS_BOTTOM);
#endif
#ifdef SDRAM_PHY_DDR4_RDIMM #ifdef SDRAM_PHY_DDR4_RDIMM
sdram_dfii_pi0_address_write((DDRX_MR_WRLVL_RESET ^ (1 << DDRX_MR_WRLVL_BIT)) ^ 0x2BF8) ; sdram_dfii_pi0_address_write((DDRX_MR_WRLVL_RESET ^ (1 << DDRX_MR_WRLVL_BIT)) ^ 0x2BF8) ;
@ -596,26 +577,7 @@ static void sdram_write_leveling_on(void) {
} }
static void sdram_write_leveling_off(void) { static void sdram_write_leveling_off(void) {
#ifndef SDRAM_PHY_CLAM_SHELL sdram_mode_register_write(DDRX_MR_WRLVL_ADDRESS, DDRX_MR_WRLVL_RESET);
sdram_dfii_pi0_address_write(DDRX_MR_WRLVL_RESET);
sdram_dfii_pi0_baddress_write(DDRX_MR_WRLVL_ADDRESS);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
#else
sdram_dfii_pi0_address_write(DDRX_MR_WRLVL_RESET);
sdram_dfii_pi0_baddress_write(DDRX_MR_WRLVL_ADDRESS);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS_TOP);
int addr = DDRX_MR_WRLVL_RESET;
int baddr = DDRX_MR_WRLVL_ADDRESS;
addr = swap_bit(addr, 3, 4);
addr = swap_bit(addr, 5, 6);
addr = swap_bit(addr, 7, 8);
addr = swap_bit(addr, 11, 13);
baddr = swap_bit(baddr, 0, 1);
sdram_dfii_pi0_address_write(addr);
sdram_dfii_pi0_baddress_write(baddr);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS_BOTTOM);
#endif
#ifdef SDRAM_PHY_DDR4_RDIMM #ifdef SDRAM_PHY_DDR4_RDIMM
sdram_dfii_pi0_address_write(DDRX_MR_WRLVL_RESET ^ 0x2BF8); sdram_dfii_pi0_address_write(DDRX_MR_WRLVL_RESET ^ 0x2BF8);