litepcie/frontend/dma: group loop index and count in loop_status register (avoid 2 register reads)
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@ -28,11 +28,9 @@ class DMARequestTable(Module, AutoCSR):
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self._value = CSRStorage(aw+lw)
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self._we = CSR()
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self._loop_prog_n = CSRStorage()
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self._index = CSRStatus(log2_int(depth))
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self._loop_status = CSRStatus(32)
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self._level = CSRStatus(log2_int(depth))
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self._loop = CSRStatus(16)
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self._flush = CSR()
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self.irq = Signal()
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# # #
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@ -41,8 +39,8 @@ class DMARequestTable(Module, AutoCSR):
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value = self._value.storage
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we = self._we.r & self._we.re
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loop_prog_n = self._loop_prog_n.storage
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index = self._index.status
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loop = self._loop.status
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loop_index = self._loop_status.status[:log2_int(depth)]
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loop_count = self._loop_status.status[16:]
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level = self._level.status
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flush = self._flush.r & self._flush.re
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@ -83,19 +81,19 @@ class DMARequestTable(Module, AutoCSR):
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source.length.eq(fifo.dout.length)
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]
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# index
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# loop_index, loop_count
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# used by the software for synchronization in
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# "loop" mode
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self.sync += \
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If(flush,
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index.eq(0),
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loop.eq(0),
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loop_index.eq(0),
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loop_count.eq(0),
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).Elif(source.stb & source.ack,
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If(fifo.dout.start,
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index.eq(0),
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loop.eq(loop+1)
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loop_index.eq(0),
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loop_count.eq(loop_count+1)
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).Else(
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index.eq(index+1)
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loop_index.eq(loop_index+1)
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)
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)
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@ -4,4 +4,7 @@
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/* dma */
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#define DMA_LOOPBACK_ENABLE 0x1
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#define DMA_TABLE_LOOP_INDEX 1 << 0
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#define DMA_TABLE_LOOP_COUNT 1 << 16
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#endif /* __HW_FLAGS_H */
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@ -268,12 +268,12 @@ static int litepcie_dma_wait(LitePCIeState *s, struct litepcie_ioctl_dma_wait *m
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for (;;) {
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/* set current buffer */
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if (s->tx_dma_started) {
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m->tx_buf_num = litepcie_readl(s, CSR_DMA_READER_TABLE_INDEX_ADDR);
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m->tx_buf_num = (litepcie_readl(s, CSR_DMA_READER_TABLE_LOOP_STATUS_ADDR) & 0xffff);
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} else {
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m->tx_buf_num = 0;
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}
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if (s->rx_dma_started) {
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m->rx_buf_num = litepcie_readl(s, CSR_DMA_WRITER_TABLE_INDEX_ADDR);
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m->rx_buf_num = (litepcie_readl(s, CSR_DMA_WRITER_TABLE_LOOP_STATUS_ADDR) & 0xfffff);
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} else {
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m->rx_buf_num = 0;
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}
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