Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

cpu/NaxRiscv improve peripheral read/write speed by staying 32 bits

This commit is contained in:
Dolu1990 2022-09-12 19:19:35 +02:00
parent 8e7fd9bc1f
commit 0a380b9c3b
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
litex/soc/cores/cpu/naxriscv/core.py
View File

@ -123,8 +123,8 @@ class NaxRiscv(CPU):
self.human_name = self.human_name
self.reset = Signal()
self.interrupt = Signal(32)
self.ibus = ibus = axi.AXILiteInterface(address_width=32, data_width=64)
self.dbus = dbus = axi.AXILiteInterface(address_width=32, data_width=64)
self.ibus = ibus = axi.AXILiteInterface(address_width=32, data_width=32)
self.dbus = dbus = axi.AXILiteInterface(address_width=32, data_width=32)
self.periph_buses = [ibus, dbus] # Peripheral buses (Connected to main SoC's bus).
self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM).
@ -228,8 +228,8 @@ class NaxRiscv(CPU):
ndir = os.path.join(vdir, "ext", "NaxRiscv")
sdir = os.path.join(vdir, "ext", "SpinalHDL")
NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git" , "main", "cb2a598a")
NaxRiscv.git_setup("SpinalHDL", sdir, "https://github.com/SpinalHDL/SpinalHDL.git", "dev" , "a130f7b7")
NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git" , "main", "15d2d10b")
NaxRiscv.git_setup("SpinalHDL", sdir, "https://github.com/SpinalHDL/SpinalHDL.git", "dev" , "5a0592d1")
gen_args = []
gen_args.append(f"--netlist-name={NaxRiscv.netlist_name}")