interconnect/wishbone: integrate Wishbone2CSR.

litex/soc/integration/soc.py

@@ -19,7 +19,6 @@ from litex.soc.cores.spi import SPIMaster
 from litex.soc.interconnect.csr import *
 from litex.soc.interconnect import csr_bus
 from litex.soc.interconnect import wishbone
-from litex.soc.interconnect import wishbone2csr
 from litex.soc.interconnect import axi
 
 logging.basicConfig(level=logging.INFO)
@@ -760,7 +759,7 @@ class SoC(Module):
         self.add_ram(name, origin, size, contents, mode="r")
 
     def add_csr_bridge(self, origin):
-        self.submodules.csr_bridge = wishbone2csr.WB2CSR(
+        self.submodules.csr_bridge = wishbone.Wishbone2CSR(
             bus_csr       = csr_bus.Interface(
             address_width = self.csr.address_width,
             data_width    = self.csr.data_width))

litex/soc/interconnect/wishbone.py

@@ -362,6 +362,40 @@ class SRAM(Module):
             If(self.bus.cyc & self.bus.stb & ~self.bus.ack, self.bus.ack.eq(1))
         ]
 
+# Wishbone To CSR ----------------------------------------------------------------------------------
+
+class Wishbone2CSR(Module):
+    def __init__(self, bus_wishbone=None, bus_csr=None):
+        self.csr = bus_csr
+        if self.csr is None:
+            # If no CSR bus provided, create it with default parameters.
+            self.csr = csr_bus.Interface()
+        self.wishbone = bus_wishbone
+        if self.wishbone is None:
+            # If no Wishbone bus provided, create it with default parameters.
+            self.wishbone = Interface()
+
+        # # #
+
+        self.comb += [
+            self.csr.dat_w.eq(self.wishbone.dat_w),
+            self.wishbone.dat_r.eq(self.csr.dat_r)
+        ]
+
+        fsm = FSM(reset_state="WRITE-READ")
+        self.submodules += fsm
+        fsm.act("WRITE-READ",
+            If(self.wishbone.cyc & self.wishbone.stb,
+                self.csr.adr.eq(self.wishbone.adr),
+                self.csr.we.eq(self.wishbone.we),
+                NextState("ACK")
+            )
+        )
+        fsm.act("ACK",
+            self.wishbone.ack.eq(1),
+            NextState("WRITE-READ")
+        )
+
 # Wishbone Cache -----------------------------------------------------------------------------------
 
 class Cache(Module):

litex/soc/interconnect/wishbone2csr.py

@@ -1,41 +0,0 @@
-# This file is Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk>
-# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
-# License: BSD
-
-from migen import *
-from migen.genlib.misc import timeline
-
-from litex.soc.interconnect import csr_bus, wishbone
-
-
-class WB2CSR(Module):
-    def __init__(self, bus_wishbone=None, bus_csr=None):
-        self.csr = bus_csr
-        if self.csr is None:
-            # If no CSR bus provided, create it with default parameters.
-            self.csr = csr_bus.Interface()
-        self.wishbone = bus_wishbone
-        if self.wishbone is None:
-            # If no Wishbone bus provided, create it with default parameters.
-            self.wishbone = wishbone.Interface()
-
-        # # #
-
-        self.comb += [
-            self.csr.dat_w.eq(self.wishbone.dat_w),
-            self.wishbone.dat_r.eq(self.csr.dat_r)
-        ]
-
-        fsm = FSM(reset_state="WRITE-READ")
-        self.submodules += fsm
-        fsm.act("WRITE-READ",
-            If(self.wishbone.cyc & self.wishbone.stb,
-                self.csr.adr.eq(self.wishbone.adr),
-                self.csr.we.eq(self.wishbone.we),
-                NextState("ACK")
-            )
-        )
-        fsm.act("ACK",
-            self.wishbone.ack.eq(1),
-            NextState("WRITE-READ")
-        )