targets/genesys2: set cmd_latency to 1.

2020-05-05 16:33:14 +02:00 · 2020-05-05 16:33:14 +02:00 · 0aa3c339cc
parent 95b57899cd
commit 0aa3c339cc
1 changed files with 2 additions and 1 deletions
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@ -56,7 +56,8 @@ class BaseSoC(SoCCore):
            self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
                memtype      = "DDR3",
                nphases      = 4,
-                sys_clk_freq = sys_clk_freq)
+                sys_clk_freq = sys_clk_freq,
+                cmd_latency  = 1)
            self.add_csr("ddrphy")
            self.add_sdram("sdram",
                phy                     = self.ddrphy,