Merge branch 'master' of https://github.com/enjoy-digital/litex into upstream

This commit is contained in:
Paul Schulz 2018-01-24 13:32:42 +10:30
commit 0ac35300c4
4 changed files with 6 additions and 6 deletions

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@ -24,7 +24,7 @@ $(OBJS_SIM): %.o: $(SRC_DIR)/%.c
.PHONY: sim .PHONY: sim
sim: mkdir $(OBJS_SIM) sim: mkdir $(OBJS_SIM)
verilator -Wno-fatal -O3 --cc dut.v --exe \ verilator -Wno-fatal -O3 --cc dut.v --top-module dut --exe \
$(SRCS_SIM_CPP) $(OBJS_SIM) \ $(SRCS_SIM_CPP) $(OBJS_SIM) \
-CFLAGS "$(CFLAGS) -I$(SRC_DIR)" \ -CFLAGS "$(CFLAGS) -I$(SRC_DIR)" \
-LDFLAGS "$(LDFLAGS)" \ -LDFLAGS "$(LDFLAGS)" \

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@ -136,7 +136,7 @@ sudo obj_dir/Vdut
class SimVerilatorToolchain: class SimVerilatorToolchain:
def build(self, platform, fragment, build_dir="build", build_name="top", def build(self, platform, fragment, build_dir="build", build_name="dut",
toolchain_path=None, serial="console", run=True, verbose=True, toolchain_path=None, serial="console", run=True, verbose=True,
sim_config=None): sim_config=None):
os.makedirs(build_dir, exist_ok=True) os.makedirs(build_dir, exist_ok=True)
@ -146,9 +146,9 @@ class SimVerilatorToolchain:
fragment = fragment.get_fragment() fragment = fragment.get_fragment()
platform.finalize(fragment) platform.finalize(fragment)
v_output = platform.get_verilog(fragment) v_output = platform.get_verilog(fragment, name=build_name)
named_sc, named_pc = platform.resolve_signals(v_output.ns) named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_output.write("dut.v") v_output.write(build_name + ".v")
include_paths = [] include_paths = []
for source in platform.sources: for source in platform.sources:

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@ -498,7 +498,7 @@ int main(int i, char **c)
#elif __or1k__ #elif __or1k__
printf("\e[1mOR1K\e[0m\n"); printf("\e[1mOR1K\e[0m\n");
#elif __riscv #elif __riscv
printf("\e[1mRISC-V\n"); printf("\e[1mRISC-V\e[0m\n");
#else #else
printf("\e[1mUnknown\e[0m\n"); printf("\e[1mUnknown\e[0m\n");
#endif #endif

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@ -1,7 +1,7 @@
TARGET_PREFIX=$(TRIPLE)- TARGET_PREFIX=$(TRIPLE)-
RM ?= rm -f RM ?= rm -f
PYTHON ?= python PYTHON ?= python3
ifeq ($(CLANG),1) ifeq ($(CLANG),1)
CC_normal := clang -target $(TRIPLE) -integrated-as CC_normal := clang -target $(TRIPLE) -integrated-as