doc: add SATA description from Erik Landström's Thesis
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@ -29,6 +29,7 @@ The full hierarchy of articles, opened to the second level, is shown below.
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introducing_litesata/index
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introducing_litesata/index
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getting_started/index
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getting_started/index
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sata/index
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phy/index
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phy/index
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core/index
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core/index
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frontend/index
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frontend/index
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.. _sata-index:
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========================
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SATA
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========================
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.. note::
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This chapter is a lightly modified version of the excellent SATA summerization found in Chapter 2 of Erik Landström's Thesis_.
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Serial Advanced Technology Attachment (SATA) is a serial link replacement of
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Parallel ATA (PATA), both standards for communication with mass storage devices.
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This high-speed serial link is a differential layer that utilizes Gigabit technology
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and 8b/10b encoding. The link supports full duplex but the protocol only permits frames
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in one direction at a time. The other non-data direction is used for flow control of the
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data stream
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.. image:: sata_layers.png
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:scale: 50 %
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:align: center
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SATA’s architecture consists of four layers, Application, Transport, Link, and Physical.
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The Application layer is responsible for overall ATA commands and of controlling SATA
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register accesses. The transport layer places control information and data to be transferred between
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the host and corresponding SATA device in a data packets. One such packet is called a frame
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information structure (FIS). The Link layer is responsible for taking data from a FIS and
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encode/decode it using 8b/10b. It also inserts control characters for flow control and calculates
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the cyclic redundancy check (CRC) for error detection. Finally the Phy layer’s task is to deliver
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and receive the encoded serial data stream on the wire.
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Dword - Data Representation
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===========================
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In the SATA standard the smallest allowed data is a Dword, its 32 bits are divided
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into four bytes. Where each pair of bytes represent a word and a pair of words
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represent a Dword. In this way it’s easy to see that odd number of bytes is not
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allowed in SATA communication.
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.. image:: byte_word_dword.png
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:scale: 50 %
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:align: center
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The Dwords can be represented by either a data Dword or a so called primitive. A
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primitive is a predefined Dword like for example start of frame (SOF) and end
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of frame (EOF).
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Primitives
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==========
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Primitives are Dwords with a purpose to enable and control the serial communication.
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They all begin with a control character followed by three other characters to
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fill up the Dword. The control character makes it easy to recognize a primitive from
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a ordinary Dword of a frame. There is 18 different primitives, all with a dedicated
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task like for example mark a frame with a SOF or to provide synchronization
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with the SYNC.
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8b/10b - Encoding
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=================
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8b/10b encoding is rather common in high speed applications, it’s used to provide
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bounded disparity but still provide enough toggling to make clock recovery possible
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(synchronize internal clock with the data stream). The bounded disparity means
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that in a string of twenty bits the difference between zeros and ones shall be -2, 0,
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or 2 and with a maximum runlength of five. The drawback is the created overhead
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of two bits per byte making the actual transfer speed of for example 1.5 Gbps link
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to 1.2 Gbps, a loss of 20 %. Since the 8b/10b extends the possible alphabet from
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256 symbols to 1024 it can provide detection and encoding of special characters
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(also called k-characters) in an easy and effective way. This is used in the SATA
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standard by encoding every primitive as such special characters.
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Out of Band Signaling
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======================
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Since SATA devices and hosts always sends junk over its differential channels,
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when it is idle (otherwise the link is considered lost), there has to be a way of
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recognizing a signal before a link has been initialized. For this SATA uses so
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called out of band signaling (OOB) to initialize a connection between a host and a
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device. The OOB mechanism supports low speed transmission over a high speed
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connection, such as a SATA link. The OOB signals are non-differential but are sent
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over a differential channel. This is possible by letting the differential transmitters
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drive their output pins to the same voltage, resulting in a reduced difference and
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when a preset threshold limit is reached the receiver can recognize the signal as
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OOB.
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.. image:: oob_signals.png
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:scale: 50 %
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:align: center
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As can be seen in the figure there are three types of (actually two
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since COMINIT and COMRESET are equal) valid OOB signals where bursts of
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six ALIGN are sent with different timing. The importance in the signaling lies
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in the timing, it does not really matter if an ALIGN or something else are sent
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because the receiver only detects the drop of voltage difference between rx+ and
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rx-. In the next figure the complete startup sequence is visualized and
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the calibration steps in it are optional to implement. The host sends COMRESET
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until the device is powered on and can respond with a COMINIT. Upon reception
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of the COMINIT the host sends a COMWAKE to the device which shall send a
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COMWAKE back. If this procedure is finished within a correct time the OOB signaling
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ends and the differential communication can proceed with determining the link speed
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(right part of the figure).
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.. image:: oob_sequence.png
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:scale: 50 %
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:align: center
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Physical Layer
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==============
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This section describes the physical interface towards the actual SATA link.
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The features of the phy can be summarized to:
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- Transmit/Receive a 1.5 Gbps, 3.0 or 6.0 Gbps differential signal
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- Speed negotiation
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- OOB detection and transmission
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- Serialize a 10, 20, or other width parallel data from the link layer
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- Extract data from the serial data stream
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- Parallelize the data stream and send it to the link layer
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- Handle spread spectrum clocking (SSC), a clock modulation technique used
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to reduce unintentional interference to radio signals
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At startup the physical layer is in its OOB state and after a link has been initiated
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it changes to Idle Bus condition and normal SATA communication is now
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supported. Since the SATA connection is noisy the physical layer detects a frame
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when it receives a SOF primitive and it will keep on listening to the incoming
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signal until an EOF primitive is received. Except from FIS the SATA traffic
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also consists of single primitives which all are easy for the PHY to recognize because
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of their starting control character.
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Link Layer
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==========
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This section describes the SATA link layer.
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The link layer’s major tasks are:
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- Flow control
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- Encapsulate FISes received from transport layer
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- CRC generation and CRC check
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- FIS scrambling and de-scrambling
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- 8b/10b encoding/decoding
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A FIS is framed between a SOF and a EOF creating the boundaries of a frame.
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The last Dword before a EOF is the CRC value for the FIS. The CRC is calculated
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by applying the 32-bits generator polynomial G(x) in Equation on every bit in
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every non-primitive Dword in a FIS and then summarize (modulo 2) all these terms
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together with the Initial Value. The CRC is fixed to value of 0x52325032.
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.. image:: crc.png
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:scale: 50 %
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:align: center
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Scrambling a FIS reduces EMI by spreading the noise over a broader frequency
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spectrum. The scrambling algorithm can be expressed as a polynomial or as a linear
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feedback shift register. The scrambling creates a pseudorandom bit pattern of the
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data that reduces EMI. The algorithm resets to a of value of 0xFFFF every time a SOF
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is encountered at the scrambler. The de-scrambler uses the same algorithm on scrambled
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data so it retakes its original form.
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.. image:: scrambler.png
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:scale: 50 %
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:align: center
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It is important that the CRC calculations are made at original data and that
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the scrambling/de-scrambling are made between the CRC and the 8b/10b encoding/decoding.
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The flow control between host and device is managed by sending
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primitives to one another telling its status (which originates from the transport
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layer). Some of these primitives can be inserted into FIS. Primitives are not
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supposed to be scrambled or added to the CRC sum. Internally the flow control
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are regulated by signaling between the layers.
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Transport Layer
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===============
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The main task for the SATA transport layer is to handle FISes and a brief description
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of the layer’s features follows:
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- Flow control
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- Error control
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- Error reporting
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- FIS construction
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- FIS decomposition
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- FIS buffering for retransmission
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There are eight types of FISes each with its specific 8-bit ID and unique header.
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FISes vary in size from 1 Dword up to 2049 Dwords. The number of bytes in a
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FIS are always a multiple of four so the transport layer has to fill up with zeros if
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there are bytes or bits missing for an entire Dword.
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The flow control in this case is only to report to the link layer that the data buffers
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are close to over- or underflow. Errors detected are supposed to be reported to
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the application layer and the detectable errors are:
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- Errors from lower layers like 8b/10b disparity error or CRC errors.
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- SATA state or protocol errors caused by standard violation.
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- Frame errors like malformed header.
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- Internal transport layer errors like buffer overflow.
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Errors are handled in different ways, for example are resending of complete FISes
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supported for all kind of FISes besides the data FISes (and the BIST FIS which
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is used typically during testing), because that would need buffers in size of 8192
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bytes (maximum supported FIS size). The max sized non-data FIS is 28 bytes so
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the costs of a large buffer can be spared.
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Command Layer
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=================
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The command layer tells the transport layer what kind of FISes to send and receive
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for each specific command and in which order those FISes are expexted to be delivered.
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.. note::
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This chapter is a lightly modified version of the excellent SATA summerization found in Chapter 2 of Erik Landström's Thesis_.
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.. _Thesis: http://www.diva-portal.org/smash/get/diva2:207798/FULLTEXT01.pdf
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@ -18,6 +18,7 @@ News
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docs/introducing_litesata/index
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docs/introducing_litesata/index
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docs/getting_started/index
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docs/getting_started/index
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docs/sata/index
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docs/phy/index
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docs/phy/index
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docs/core/index
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docs/core/index
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docs/frontend/index
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docs/frontend/index
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