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soc/cores/hyperbus: Add comment to allow switching to SDRTristate.

This commit is contained in:
Florent Kermarrec 2024-08-20 22:05:38 +02:00
parent 60f83b71fa
commit 0b028d3956
1 changed files with 8 additions and 8 deletions
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16
litex/soc/cores/hyperbus.py
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@ -91,20 +91,20 @@ class HyperRAM(LiteXModule):
# ---------- # ----------
dq = self.add_tristate(pads.dq, register=False) if not hasattr(pads.dq, "oe") else pads.dq dq = self.add_tristate(pads.dq, register=False) if not hasattr(pads.dq, "oe") else pads.dq
rwds = self.add_tristate(pads.rwds, register=False) if not hasattr(pads.rwds, "oe") else pads.rwds rwds = self.add_tristate(pads.rwds, register=False) if not hasattr(pads.rwds, "oe") else pads.rwds
self.comb += [ self.comb += [ # FIXME: Try to move to sync to allow switching to SDRTristate.
# DQ O/OE. # DQ.
dq.o.eq( dq_o), dq.o.eq( dq_o),
dq.oe.eq(dq_oe), dq.oe.eq(dq_oe),
# RWDS O/OE. # RWDS.
rwds.o.eq( rwds_o), rwds.o.eq( rwds_o),
rwds.oe.eq(rwds_oe), rwds.oe.eq(rwds_oe),
] ]
self.sync += [ self.sync += [
# DQ I. # DQ.
dq_i.eq(dq.i), dq_i.eq(dq.i),
# RWDS I. # RWDS.
rwds_i.eq(rwds.i) rwds_i.eq(rwds.i)
] ]
@ -165,14 +165,14 @@ class HyperRAM(LiteXModule):
self.sync += If(clk_phase[0] == 0, sr.eq(sr_next)) # Shift on 0°/180° (and sampled on 90°/270°). self.sync += If(clk_phase[0] == 0, sr.eq(sr_next)) # Shift on 0°/180° (and sampled on 90°/270°).
# Data Shift-Out Register ------------------------------------------------------------------ # Data Shift-Out Register ------------------------------------------------------------------
self.comb += bus.dat_r.eq(sr_next)
self.comb += [ self.comb += [
bus.dat_r.eq(sr_next),
# Command/Address: 8-bit. # Command/Address: 8-bit.
If(ca_oe, If(ca_oe,
dq_o.eq(sr[-8:]), dq_o.eq(sr[-8:])
# Data: dw-bit. # Data: dw-bit.
).Else( ).Else(
dq_o.eq(sr[-dw:]), dq_o.eq(sr[-dw:])
) )
] ]