liteeth: do MII/GMII detection in gateware for gmii_mii phy
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07b7c2a13f
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0b1a2e1022
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@ -83,58 +83,78 @@ class LiteEthPHYGMIIMIIRX(Module):
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class LiteEthGMIIMIIModeDetection(Module, AutoCSR):
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def __init__(self):
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self._reset = CSRStorage()
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self._counter = CSRStatus(32)
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self._mode = CSRStorage()
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def __init__(self, clk_freq):
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self.mode = Signal()
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self._mode = CSRStatus()
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# # #
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# Note:
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# For now mode detection is done with gateware and software.
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# We will probably do it in gateware in the future
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# (we will need to pass clk_freq parameter to PHY)
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mode = Signal()
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update_mode = Signal()
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self.sync += \
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If(update_mode,
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self.mode.eq(mode)
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)
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self.comb += self._mode.status.eq(self.mode)
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# Principle:
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# sys_clk >= 125MHz
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# eth_rx <= 125Mhz
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# We generate a pulse in eth_rx clock domain that increments
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# a counter in sys_clk domain.
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# We generate ticks every 1024 clock cycles in eth_rx domain
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# and measure ticks period in sys_clk domain.
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# Generate a pulse every 4 clock cycles (eth_rx clock domain)
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eth_pulse = Signal()
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eth_counter = Signal(2)
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# Generate a tick every 1024 clock cycles (eth_rx clock domain)
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eth_tick = Signal()
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eth_counter = Signal(10)
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self.sync.eth_rx += eth_counter.eq(eth_counter + 1)
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self.comb += eth_pulse.eq(eth_counter == 0)
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self.comb += eth_tick.eq(eth_counter == 0)
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# Synchronize pulse (sys clock domain)
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sys_pulse = Signal()
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# Synchronize tick (sys clock domain)
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sys_tick = Signal()
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eth_ps = PulseSynchronizer("eth_rx", "sys")
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self.comb += [
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eth_ps.i.eq(eth_pulse),
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sys_pulse.eq(eth_ps.o)
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eth_ps.i.eq(eth_tick),
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sys_tick.eq(eth_ps.o)
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]
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self.submodules += eth_ps
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# Count pulses (sys clock domain)
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counter = Counter(32)
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self.submodules += counter
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self.comb += [
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counter.reset.eq(self._reset.storage),
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counter.ce.eq(sys_pulse)
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]
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self.comb += self._counter.status.eq(counter.value)
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# sys_clk domain counter
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sys_counter = Counter(24)
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self.submodules += sys_counter
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# Output mode
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self.comb += self.mode.eq(self._mode.storage)
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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sys_counter.reset.eq(1),
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If(sys_tick,
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NextState("COUNT")
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)
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)
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fsm.act("COUNT",
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sys_counter.ce.eq(1),
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If(sys_tick,
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NextState("DETECTION")
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)
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)
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fsm.act("DETECTION",
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update_mode.eq(1),
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# if freq < 125MHz-5% use MII mode
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If(sys_counter.value > int((clk_freq/125000000)*1024*1.05),
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mode.eq(1)
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# if freq >= 125MHz-5% use GMII mode
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).Else(
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mode.eq(0)
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),
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NextState("IDLE")
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)
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class LiteEthPHYGMIIMII(Module, AutoCSR):
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def __init__(self, clock_pads, pads, with_hw_init_reset=True):
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def __init__(self, clock_pads, pads, clk_freq, with_hw_init_reset=True):
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self.dw = 8
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# Note: we can use GMII CRG since it also handles tx clock pad used for MII
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self.submodules.mode_detection = LiteEthGMIIMIIModeDetection()
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self.submodules.mode_detection = LiteEthGMIIMIIModeDetection(clk_freq)
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mode = self.mode_detection.mode
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self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset, mode == modes["MII"])
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self.submodules.tx = RenameClockDomains(LiteEthPHYGMIIMIITX(pads, mode), "eth_tx")
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@ -497,20 +497,15 @@ static int test_user_abort(void)
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static void boot_sequence(void)
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{
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int eth_ok;
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if(test_user_abort()) {
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#ifdef FLASH_BOOT_ADDRESS
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flashboot();
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#endif
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serialboot();
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#ifdef CSR_ETHPHY_MODE_DETECTION_MODE_ADDR
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eth_ok = eth_mode_detection();
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#else
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eth_ok = 1;
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eth_mode();
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#endif
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#ifdef CSR_ETHMAC_BASE
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if (eth_ok)
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netboot();
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#endif
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printf("No boot medium found\n");
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@ -531,7 +526,7 @@ int main(int i, char **c)
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crcbios();
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id_print();
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#ifdef CSR_ETHMAC_BASE
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ethreset();
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eth_init();
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#endif
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#ifdef CSR_SDRAM_BASE
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sdr_ok = sdrinit();
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@ -14,7 +14,7 @@ int microudp_send(unsigned short src_port, unsigned short dst_port, unsigned int
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void microudp_set_callback(udp_callback callback);
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void microudp_service(void);
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void ethreset(void);
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int eth_mode_detection(void);
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void eth_init(void);
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void eth_mode(void);
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#endif /* __MICROUDP_H */
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@ -433,7 +433,7 @@ static void busy_wait(unsigned int ds)
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while(timer0_value_read()) timer0_update_value_write(1);
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}
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void ethreset(void)
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void eth_init(void)
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{
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ethphy_crg_reset_write(0);
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busy_wait(2);
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@ -445,50 +445,15 @@ void ethreset(void)
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}
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#ifdef CSR_ETHPHY_MODE_DETECTION_MODE_ADDR
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static int eth_test_frequency(unsigned int freq, unsigned int target, unsigned int margin)
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void eth_mode(void)
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{
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if (freq < (target - margin))
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return 0;
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else if (freq > (target + margin))
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return 0;
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else
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return 1;
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}
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int eth_mode_detection(void)
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{
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unsigned int frequency;
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ethphy_mode_detection_reset_write(1);
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busy_wait(1);
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ethphy_mode_detection_reset_write(0);
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busy_wait(1);
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frequency = ethphy_mode_detection_counter_read()*4*10;
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ethphy_mode_detection_reset_write(1);
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printf("Ethernet phy mode: ");
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/* 10Mbps */
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if(eth_test_frequency(frequency, 2500000, 1000000)) {
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ethphy_mode_detection_mode_write(1);
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printf("10Mbps (MII)\n");
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return 1;
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/* 100Mbps */
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} else if(eth_test_frequency(frequency, 25000000, 1000000)) {
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ethphy_mode_detection_mode_write(1);
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printf("100Mbps (MII)\n");
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return 1;
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/* 1Gbps */
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} else if(eth_test_frequency(frequency, 125000000, 1000000)) {
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ethphy_mode_detection_mode_write(0);
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printf("1Gbps (GMII)\n");
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return 1;
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/* Failed */
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} else {
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printf("Failed to detect link speed\n");
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return 0;
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}
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if (ethphy_mode_detection_mode_read())
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printf("MII");
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else
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printf("GMII");
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printf("\n");
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}
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#endif
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#endif
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@ -122,7 +122,7 @@ class MiniSoC(BaseSoC):
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def __init__(self, platform, **kwargs):
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BaseSoC.__init__(self, platform, **kwargs)
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self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"))
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self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"), clk_freq=self.clk_freq)
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self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
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self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
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self.add_memory_region("ethmac", self.mem_map["ethmac"]+self.shadow_address, 0x2000)
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