sim: pass extra keyword arguments to Verilog converter

doc/index.rst

@@ -474,6 +474,7 @@ The constructor of the ``Simulator`` object takes the following parameters:
 #. A simulator runner object (see :ref:`simrunner`).
 #. A top-level object (see :ref:`toplevel`). With the default value of ``None``, the simulator creates a default top-level object itself.
 #. The name of the UNIX domain socket used to communicate with the external simulator through the VPI plug-in (default: "simsocket").
+#. Additional keyword arguments (if any) are passed to the Verilog conversion function.
 
 Running the simulation
 ======================

migen/sim/generic.py

@@ -68,7 +68,7 @@ end
 		return r
 
 class Simulator:
-	def __init__(self, fragment, sim_runner, top_level=None, sockaddr="simsocket"):
+	def __init__(self, fragment, sim_runner, top_level=None, sockaddr="simsocket", **vopts):
 		self.fragment = fragment
 		if top_level is None:
 			self.top_level = TopLevel()
@@ -85,7 +85,8 @@ class Simulator:
 			name=self.top_level.dut_type,
 			clk_signal=clk_signal,
 			rst_signal=rst_signal,
-			return_ns=True)
+			return_ns=True,
+			**vopts)
 		
 		self.cycle_counter = -1
 		self.interrupt = False