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sim: pass extra keyword arguments to Verilog converter

This commit is contained in:
Sebastien Bourdeauducq 2012-04-30 16:38:17 -05:00
parent 6a52e44d09
commit 0b62e573ae
2 changed files with 4 additions and 2 deletions
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1
doc/index.rst
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@ -474,6 +474,7 @@ The constructor of the ``Simulator`` object takes the following parameters:
#. A simulator runner object (see :ref:`simrunner`). #. A simulator runner object (see :ref:`simrunner`).
#. A top-level object (see :ref:`toplevel`). With the default value of ``None``, the simulator creates a default top-level object itself. #. A top-level object (see :ref:`toplevel`). With the default value of ``None``, the simulator creates a default top-level object itself.
#. The name of the UNIX domain socket used to communicate with the external simulator through the VPI plug-in (default: "simsocket"). #. The name of the UNIX domain socket used to communicate with the external simulator through the VPI plug-in (default: "simsocket").
#. Additional keyword arguments (if any) are passed to the Verilog conversion function.
Running the simulation Running the simulation
====================== ======================

5
migen/sim/generic.py
View File

@ -68,7 +68,7 @@ end
return r return r
class Simulator: class Simulator:
def __init__(self, fragment, sim_runner, top_level=None, sockaddr="simsocket"): def __init__(self, fragment, sim_runner, top_level=None, sockaddr="simsocket", **vopts):
self.fragment = fragment self.fragment = fragment
if top_level is None: if top_level is None:
self.top_level = TopLevel() self.top_level = TopLevel()
@ -85,7 +85,8 @@ class Simulator:
name=self.top_level.dut_type, name=self.top_level.dut_type,
clk_signal=clk_signal, clk_signal=clk_signal,
rst_signal=rst_signal, rst_signal=rst_signal,
return_ns=True) return_ns=True,
**vopts)
self.cycle_counter = -1 self.cycle_counter = -1
self.interrupt = False self.interrupt = False