fix uart selection when opening wishbone
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1a07116ab1
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0bc1cd6f77
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@ -23,13 +23,13 @@ class Uart2Wishbone:
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self.uart.open()
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self.uart.flushInput()
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try:
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wb.regs.uart2wb_sel.write(1)
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self.regs.uart2wb_sel.write(1)
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except:
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pass
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def close(self):
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try:
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wb.regs.uart2wb_sel.write(0)
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self.regs.uart2wb_sel.write(0)
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except:
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pass
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self.uart.close()
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@ -1,7 +1,17 @@
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import sys
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import datetime
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from miscope.std.misc import *
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def dec2bin(d, nb=0):
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if d=="x":
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return "x"*nb
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elif d==0:
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b="0"
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else:
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b=""
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while d!=0:
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b="01"[d&1]+b
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d=d>>1
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return b.zfill(nb)
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def get_bits(values, width, low, high=None):
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r = []
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