soc: remove is_sim function
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905be50451
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@ -15,12 +15,6 @@ from misoclib.cpu.peripherals import identifier, timer
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def mem_decoder(address, start=26, end=29):
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def mem_decoder(address, start=26, end=29):
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return lambda a: a[start:end] == ((address >> (start+2)) & (2**(end-start))-1)
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return lambda a: a[start:end] == ((address >> (start+2)) & (2**(end-start))-1)
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def is_sim(platform):
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if hasattr(platform, "is_sim"):
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return platform.is_sim
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else:
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return False
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class SoC(Module):
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class SoC(Module):
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csr_map = {
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csr_map = {
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"crg": 0, # user
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"crg": 0, # user
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@ -114,7 +108,7 @@ class SoC(Module):
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self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone)
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self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone)
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if with_uart:
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if with_uart:
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if is_sim(platform):
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if getattr(platform, "is_sim", False):
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self.submodules.uart_phy = UARTPHYSim(platform.request("serial"))
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self.submodules.uart_phy = UARTPHYSim(platform.request("serial"))
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else:
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else:
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self.submodules.uart_phy = UARTPHYSerial(platform.request("serial"), clk_freq, uart_baudrate)
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self.submodules.uart_phy = UARTPHYSerial(platform.request("serial"), clk_freq, uart_baudrate)
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