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soc: remove is_sim function

This commit is contained in:
Florent Kermarrec 2015-03-03 10:15:11 +01:00
parent 905be50451
commit 0bcd6daf63
1 changed files with 1 additions and 7 deletions
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8
misoclib/soc/__init__.py
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@ -15,12 +15,6 @@ from misoclib.cpu.peripherals import identifier, timer
def mem_decoder(address, start=26, end=29):
return lambda a: a[start:end] == ((address >> (start+2)) & (2**(end-start))-1)
def is_sim(platform):
if hasattr(platform, "is_sim"):
return platform.is_sim
else:
return False
class SoC(Module):
csr_map = {
"crg": 0, # user
@ -114,7 +108,7 @@ class SoC(Module):
self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone)
if with_uart:
if is_sim(platform):
if getattr(platform, "is_sim", False):
self.submodules.uart_phy = UARTPHYSim(platform.request("serial"))
else:
self.submodules.uart_phy = UARTPHYSerial(platform.request("serial"), clk_freq, uart_baudrate)