clock/efinix_trion: Add n parameter, rename pll_name to name.
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7aac228690
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0c028d1614
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@ -17,30 +17,30 @@ class Open(Signal): pass
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class TRIONPLL(Module):
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nclkouts_max = 4
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def __init__(self, platform):
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def __init__(self, platform, n=0):
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self.logger = logging.getLogger("TRIONPLL")
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self.logger.info("Creating TRIONPLL.".format())
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self.platform = platform
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self.nclkouts = 0
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self.pll_name = "pll0" # FIXME: Add support for multiple PLLs.
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self.reset = Signal()
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self.locked = Signal()
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self.name = f"pll{n}"
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# Create PLL block.
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block = {}
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block["type"] = "PLL"
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block["name"] = self.pll_name
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block["name"] = self.name
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block["clk_out"] = []
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block["locked"] = self.pll_name + "_locked"
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block["rstn"] = self.pll_name + "_rstn"
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block["locked"] = self.name + "_locked"
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block["rstn"] = self.name + "_rstn"
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self.platform.toolchain.ifacewriter.blocks.append(block)
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# Connect PLL's rstn/locked.
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self.comb += self.platform.add_iface_io(self.pll_name + "_rstn").eq(~self.reset)
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self.comb += self.locked.eq(self.platform.add_iface_io(self.pll_name + "_locked"))
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self.comb += self.platform.add_iface_io(self.name + "_rstn").eq(~self.reset)
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self.comb += self.locked.eq(self.platform.add_iface_io(self.name + "_locked"))
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def register_clkin(self, clkin, freq, name=""):
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block = self.platform.toolchain.ifacewriter.get_block(self.pll_name)
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block = self.platform.toolchain.ifacewriter.get_block(self.name)
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block["input_clock_name"] = self.platform.get_pin_name(clkin)
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@ -83,7 +83,7 @@ class TRIONPLL(Module):
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def create_clkout(self, cd, freq, phase=0, margin=1e-2, name="", with_reset=False):
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assert self.nclkouts < self.nclkouts_max
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clk_out_name = "{}_CLKOUT{}".format(self.pll_name, self.nclkouts) if name == "" else name
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clk_out_name = "{}_CLKOUT{}".format(self.name, self.nclkouts) if name == "" else name
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if cd is not None:
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self.platform.add_extension([(clk_out_name, 0, Pins(1))])
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@ -95,11 +95,11 @@ class TRIONPLL(Module):
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self.nclkouts += 1
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block = self.platform.toolchain.ifacewriter.get_block(self.pll_name)
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block = self.platform.toolchain.ifacewriter.get_block(self.name)
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block["clk_out"].append([clk_out_name, freq, phase, margin])
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def extra(self, extra):
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block = self.platform.toolchain.ifacewriter.get_block(self.pll_name)
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block = self.platform.toolchain.ifacewriter.get_block(self.name)
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block["extra"] = extra
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def compute_config(self):
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