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clock/efinix_trion: Add n parameter, rename pll_name to name.

This commit is contained in:
Florent Kermarrec 2021-11-09 11:19:27 +01:00
parent 7aac228690
commit 0c028d1614
1 changed files with 11 additions and 11 deletions
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22
litex/soc/cores/clock/efinix_trion.py
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@ -17,30 +17,30 @@ class Open(Signal): pass
class TRIONPLL(Module): class TRIONPLL(Module):
nclkouts_max = 4 nclkouts_max = 4
def __init__(self, platform): def __init__(self, platform, n=0):
self.logger = logging.getLogger("TRIONPLL") self.logger = logging.getLogger("TRIONPLL")
self.logger.info("Creating TRIONPLL.".format()) self.logger.info("Creating TRIONPLL.".format())
self.platform = platform self.platform = platform
self.nclkouts = 0 self.nclkouts = 0
self.pll_name = "pll0" # FIXME: Add support for multiple PLLs.
self.reset = Signal() self.reset = Signal()
self.locked = Signal() self.locked = Signal()
self.name = f"pll{n}"
# Create PLL block. # Create PLL block.
block = {} block = {}
block["type"] = "PLL" block["type"] = "PLL"
block["name"] = self.pll_name block["name"] = self.name
block["clk_out"] = [] block["clk_out"] = []
block["locked"] = self.pll_name + "_locked" block["locked"] = self.name + "_locked"
block["rstn"] = self.pll_name + "_rstn" block["rstn"] = self.name + "_rstn"
self.platform.toolchain.ifacewriter.blocks.append(block) self.platform.toolchain.ifacewriter.blocks.append(block)
# Connect PLL's rstn/locked. # Connect PLL's rstn/locked.
self.comb += self.platform.add_iface_io(self.pll_name + "_rstn").eq(~self.reset) self.comb += self.platform.add_iface_io(self.name + "_rstn").eq(~self.reset)
self.comb += self.locked.eq(self.platform.add_iface_io(self.pll_name + "_locked")) self.comb += self.locked.eq(self.platform.add_iface_io(self.name + "_locked"))
def register_clkin(self, clkin, freq, name=""): def register_clkin(self, clkin, freq, name=""):
block = self.platform.toolchain.ifacewriter.get_block(self.pll_name) block = self.platform.toolchain.ifacewriter.get_block(self.name)
block["input_clock_name"] = self.platform.get_pin_name(clkin) block["input_clock_name"] = self.platform.get_pin_name(clkin)
@ -83,7 +83,7 @@ class TRIONPLL(Module):
def create_clkout(self, cd, freq, phase=0, margin=1e-2, name="", with_reset=False): def create_clkout(self, cd, freq, phase=0, margin=1e-2, name="", with_reset=False):
assert self.nclkouts < self.nclkouts_max assert self.nclkouts < self.nclkouts_max
clk_out_name = "{}_CLKOUT{}".format(self.pll_name, self.nclkouts) if name == "" else name clk_out_name = "{}_CLKOUT{}".format(self.name, self.nclkouts) if name == "" else name
if cd is not None: if cd is not None:
self.platform.add_extension([(clk_out_name, 0, Pins(1))]) self.platform.add_extension([(clk_out_name, 0, Pins(1))])
@ -95,11 +95,11 @@ class TRIONPLL(Module):
self.nclkouts += 1 self.nclkouts += 1
block = self.platform.toolchain.ifacewriter.get_block(self.pll_name) block = self.platform.toolchain.ifacewriter.get_block(self.name)
block["clk_out"].append([clk_out_name, freq, phase, margin]) block["clk_out"].append([clk_out_name, freq, phase, margin])
def extra(self, extra): def extra(self, extra):
block = self.platform.toolchain.ifacewriter.get_block(self.pll_name) block = self.platform.toolchain.ifacewriter.get_block(self.name)
block["extra"] = extra block["extra"] = extra
def compute_config(self): def compute_config(self):