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wishbone/DownConverter: fix read datapath when access is skipped because sel = 0. 

We also need to shift dat_r when acess is skipped.
This commit is contained in:
Florent Kermarrec 2020-06-22 13:37:14 +02:00
parent 84617b585b
commit 0c0689f444
1 changed files with 7 additions and 7 deletions
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12
litex/soc/interconnect/wishbone.py
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@ -235,6 +235,7 @@ class DownConverter(Module):
# # #
skip = Signal()
counter = Signal(max=ratio)
# Control Path
@ -252,12 +253,11 @@ class DownConverter(Module):
slave.adr.eq(Cat(counter, master.adr)),
Case(counter, {i: slave.sel.eq(master.sel[i*dw_to//8:]) for i in range(ratio)}),
If(master.stb & master.cyc,
If(slave.sel != 0,
skip.eq(slave.sel == 0),
slave.we.eq(master.we),
slave.cyc.eq(1),
slave.stb.eq(1),
),
If(slave.ack | (slave.sel == 0),
slave.cyc.eq(~skip),
slave.stb.eq(~skip),
If(slave.ack | skip,
NextValue(counter, counter + 1),
If(counter == (ratio - 1),
master.ack.eq(1),
@ -273,7 +273,7 @@ class DownConverter(Module):
# Read Datapath
dat_r = Signal(dw_from, reset_less=True)
self.comb += master.dat_r.eq(Cat(dat_r[dw_to:], slave.dat_r))
self.sync += If(slave.ack, dat_r.eq(master.dat_r))
self.sync += If(slave.ack | skip, dat_r.eq(master.dat_r))
class Converter(Module):