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test/fifo: do not use Record

This commit is contained in:
Sebastien Bourdeauducq 2015-09-30 17:06:31 +08:00
parent 4451bb20e5
commit 0c1e1c9769
1 changed files with 8 additions and 12 deletions
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20
migen/test/test_fifo.py
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@ -10,19 +10,15 @@ from migen.test.support import SimCase
class SyncFIFOCase(SimCase, unittest.TestCase):
class TestBench(Module):
def __init__(self):
self.submodules.dut = SyncFIFO([("a", 32), ("b", 32)], 2)
self.submodules.dut = SyncFIFO(64, 2)
self.sync += [
If(self.dut.we & self.dut.writable,
self.dut.din.a.eq(self.dut.din.a + 1),
self.dut.din.b.eq(self.dut.din.b + 2)
self.dut.din[:32].eq(self.dut.din[:32] + 1),
self.dut.din[32:].eq(self.dut.din[32:] + 2)
)
]
def test_sizes(self):
self.assertEqual(len(self.tb.dut.din_bits), 64)
self.assertEqual(len(self.tb.dut.dout_bits), 64)
def test_run_sequence(self):
seq = list(range(20))
def gen():
@ -36,8 +32,8 @@ class SyncFIFOCase(SimCase, unittest.TestCase):
i = seq.pop(0)
except IndexError:
break
self.assertEqual((yield self.tb.dut.dout.a), i)
self.assertEqual((yield self.tb.dut.dout.b), i*2)
self.assertEqual((yield self.tb.dut.dout[:32]), i)
self.assertEqual((yield self.tb.dut.dout[32:]), i*2)
yield
self.run_with(gen())
@ -48,13 +44,13 @@ class SyncFIFOCase(SimCase, unittest.TestCase):
yield self.tb.dut.we.eq(cycle % 2 == 0)
yield self.tb.dut.re.eq(cycle % 7 == 0)
yield self.tb.dut.replace.eq(
(yield self.tb.dut.din.a) % 5 == 1)
(yield self.tb.dut.din[:32]) % 5 == 1)
if (yield self.tb.dut.readable) and (yield self.tb.dut.re):
try:
i = seq.pop(0)
except IndexError:
break
self.assertEqual((yield self.tb.dut.dout.a), i)
self.assertEqual((yield self.tb.dut.dout.b), i*2)
self.assertEqual((yield self.tb.dut.dout[:32]), i)
self.assertEqual((yield self.tb.dut.dout[32:]), i*2)
yield
self.run_with(gen())