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cores/clock/S7PLL: fix -1/-3 speedgrade vco max freq swap

This commit is contained in:
Florent Kermarrec 2019-08-09 09:27:32 +02:00
parent 82cd557c24
commit 0c287b11ba
1 changed files with 2 additions and 2 deletions
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4
litex/soc/cores/clock.py
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@ -214,9 +214,9 @@ class S7PLL(XilinxClocking):
XilinxClocking.__init__(self) XilinxClocking.__init__(self)
self.divclk_divide_range = (1, 56+1) self.divclk_divide_range = (1, 56+1)
self.vco_freq_range = { self.vco_freq_range = {
-1: (800e6, 2133e6), -1: (800e6, 1600e6),
-2: (800e6, 1866e6), -2: (800e6, 1866e6),
-3: (800e6, 1600e6), -3: (800e6, 2133e6),
}[speedgrade] }[speedgrade]
def do_finalize(self): def do_finalize(self):