cores/clock/S7PLL: fix -1/-3 speedgrade vco max freq swap

2019-08-09 09:27:32 +02:00 · 2019-08-09 09:27:32 +02:00 · 0c287b11ba
parent 82cd557c24
commit 0c287b11ba
1 changed files with 2 additions and 2 deletions
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@ -214,9 +214,9 @@ class S7PLL(XilinxClocking):
        XilinxClocking.__init__(self)
        self.divclk_divide_range = (1, 56+1)
        self.vco_freq_range = {
-            -1: (800e6, 2133e6),
+            -1: (800e6, 1600e6),
            -2: (800e6, 1866e6),
-            -3: (800e6, 1600e6),
+            -3: (800e6, 2133e6),
        }[speedgrade]

    def do_finalize(self):