Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

litex_sim: adding spi-flash option to simulation 

Signed-off-by: Paweł Sagan <psagan@antmicro.com>
This commit is contained in:
Pawel Sagan 2021-09-01 10:19:12 +02:00
parent 8c50366d15
commit 0c91bb7b96
1 changed files with 27 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
litex/tools/litex_sim.py
View File

@ -74,6 +74,19 @@ _io = [
Subsignal("sda_out", Pins(1)),
Subsignal("sda_in", Pins(1)),
),
("spiflash", 0,
Subsignal("cs_n", Pins(1)),
Subsignal("clk", Pins(1)),
Subsignal("mosi", Pins(1)),
Subsignal("miso", Pins(1)),
Subsignal("wp", Pins(1)),
Subsignal("hold", Pins(1)),
),
("spiflash4x", 0,
Subsignal("cs_n", Pins(1)),
Subsignal("clk", Pins(1)),
Subsignal("dq", Pins(4)),
),
]
# Platform -----------------------------------------------------------------------------------------
@ -85,6 +98,9 @@ class Platform(SimPlatform):
# Simulation SoC -----------------------------------------------------------------------------------
class SimSoC(SoCCore):
mem_map = {
"spiflash" : 0x80000000,
}
def __init__(self,
with_sdram = False,
with_ethernet = False,
@ -99,6 +115,7 @@ class SimSoC(SoCCore):
sdram_verbosity = 0,
with_i2c = False,
with_sdcard = False,
with_spi_flash = False,
sim_debug = False,
trace_reset_on = False,
**kwargs):
@ -232,6 +249,14 @@ class SimSoC(SoCCore):
if with_sdcard:
self.add_sdcard("sdcard", use_emulator=True)
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import S25FL128L
from litespi.opcodes import SpiNorFlashOpCodes as Codes
platform.add_sources(os.path.abspath(os.path.dirname(__file__)), "../build/sim/verilog/iddr_verilog.v")
platform.add_sources(os.path.abspath(os.path.dirname(__file__)), "../build/sim/verilog/oddr_verilog.v")
self.add_spi_flash(mode="4x", module=S25FL128L(Codes.READ_1_1_4), with_master=True)
# Simulation debugging ----------------------------------------------------------------------
if sim_debug:
platform.add_debug(self, reset=1 if trace_reset_on else 0)
@ -295,6 +320,7 @@ def sim_args(parser):
parser.add_argument("--with-analyzer", action="store_true", help="Enable Analyzer support")
parser.add_argument("--with-i2c", action="store_true", help="Enable I2C support")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed)")
parser.add_argument("--trace", action="store_true", help="Enable Tracing")
parser.add_argument("--trace-fst", action="store_true", help="Enable FST tracing (default=VCD)")
parser.add_argument("--trace-start", default="0", help="Time to start tracing (ps)")
@ -354,6 +380,7 @@ def main():
with_analyzer = args.with_analyzer,
with_i2c = args.with_i2c,
with_sdcard = args.with_sdcard,
with_spi_flash = args.with_spi_flash,
sim_debug = args.sim_debug,
trace_reset_on = trace_start > 0 or trace_end > 0,
sdram_init = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu.endianness),