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litesata: add mirroring
This commit is contained in:
Florent Kermarrec
parent
c3716296ae
commit
0d1a7b9315
5 changed files with 402 additions and 0 deletions
98
misoclib/mem/litesata/example_designs/targets/mirroring.py
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98
misoclib/mem/litesata/example_designs/targets/mirroring.py
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@ -0,0 +1,98 @@
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from misoclib.mem.litesata.common import *
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from migen.genlib.cdc import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.bank.description import *
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from misoclib.soc import SoC
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from misoclib.tools.litescope.common import *
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from misoclib.tools.litescope.frontend.la import LiteScopeLA
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from misoclib.tools.litescope.core.port import LiteScopeTerm
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from misoclib.com.uart.bridge import UARTWishboneBridge
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from misoclib.mem.litesata.common import *
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from misoclib.mem.litesata.phy import LiteSATAPHY
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from misoclib.mem.litesata.core import LiteSATACore
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from misoclib.mem.litesata.frontend.crossbar import LiteSATACrossbar
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from misoclib.mem.litesata.frontend.mirroring import LiteSATAMirroring
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from misoclib.mem.litesata.frontend.bist import LiteSATABIST
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from misoclib.mem.litesata.example_designs.targets.bist import CRG, StatusLeds
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class MirroringSoC(SoC, AutoCSR):
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default_platform = "kc705"
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csr_map = {
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"sata_bist0": 16,
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"sata_bist1": 17,
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"sata_bist2": 18,
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"sata_bist3": 19,
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}
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csr_map.update(SoC.csr_map)
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def __init__(self, platform):
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clk_freq = 166*1000000
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SoC.__init__(self, platform, clk_freq,
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cpu_type="none",
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with_csr=True, csr_data_width=32,
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with_uart=False,
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with_identifier=True,
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with_timer=False
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)
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self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
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self.add_wb_master(self.cpu_or_bridge.wishbone)
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self.submodules.crg = CRG(platform)
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# SATA PHYs
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sata_phy0 = LiteSATAPHY(platform.device, platform.request("sata_clocks"), platform.request("sata", 0), "sata_gen2", clk_freq)
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sata_phy1 = LiteSATAPHY(platform.device, sata_phy0.crg.refclk, platform.request("sata", 1), "sata_gen2", clk_freq)
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sata_phy2 = LiteSATAPHY(platform.device, sata_phy0.crg.refclk, platform.request("sata", 2), "sata_gen2", clk_freq)
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sata_phy3 = LiteSATAPHY(platform.device, sata_phy0.crg.refclk, platform.request("sata", 3), "sata_gen2", clk_freq)
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sata_phys = [sata_phy0, sata_phy1, sata_phy2, sata_phy3]
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for i, sata_phy in enumerate(sata_phys):
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sata_phy = RenameClockDomains(sata_phy, {"sata_rx": "sata_rx{}".format(str(i)),
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"sata_tx": "sata_tx{}".format(str(i))})
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setattr(self.submodules, "sata_phy{}".format(str(i)), sata_phy)
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# SATA Cores
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self.submodules.sata_core0 = LiteSATACore(self.sata_phy0)
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self.submodules.sata_core1 = LiteSATACore(self.sata_phy1)
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self.submodules.sata_core2 = LiteSATACore(self.sata_phy2)
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self.submodules.sata_core3 = LiteSATACore(self.sata_phy3)
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sata_cores = [self.sata_core0, self.sata_core1, self.sata_core2, self.sata_core3]
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# SATA Frontend
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self.submodules.sata_mirroring = LiteSATAMirroring(sata_cores)
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self.submodules.sata_crossbar0 = LiteSATACrossbar(self.sata_mirroring.ports[0])
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self.submodules.sata_crossbar1 = LiteSATACrossbar(self.sata_mirroring.ports[1])
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self.submodules.sata_crossbar2 = LiteSATACrossbar(self.sata_mirroring.ports[2])
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self.submodules.sata_crossbar3 = LiteSATACrossbar(self.sata_mirroring.ports[3])
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# SATA Application
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self.submodules.sata_bist0 = LiteSATABIST(self.sata_crossbar0, with_csr=True)
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self.submodules.sata_bist1 = LiteSATABIST(self.sata_crossbar1, with_csr=True)
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self.submodules.sata_bist2 = LiteSATABIST(self.sata_crossbar2, with_csr=True)
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self.submodules.sata_bist3 = LiteSATABIST(self.sata_crossbar3, with_csr=True)
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# Status Leds
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self.submodules.status_leds = StatusLeds(platform, sata_phys)
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platform.add_platform_command("""
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create_clock -name sys_clk -period 6 [get_nets sys_clk]
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""")
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for i in range(len(sata_phys)):
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platform.add_platform_command("""
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create_clock -name {sata_rx_clk} -period 6.66 [get_nets {sata_rx_clk}]
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create_clock -name {sata_tx_clk} -period 6.66 [get_nets {sata_tx_clk}]
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set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_rx_clk}]
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set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_tx_clk}]
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set_false_path -from [get_clocks {sata_rx_clk}] -to [get_clocks sys_clk]
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set_false_path -from [get_clocks {sata_tx_clk}] -to [get_clocks sys_clk]
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""".format(sata_rx_clk="sata_rx{}_clk".format(str(i)),
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sata_tx_clk="sata_tx{}_clk".format(str(i))))
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default_subtarget = MirroringSoC
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43
misoclib/mem/litesata/example_designs/test/test_mirroring.py
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43
misoclib/mem/litesata/example_designs/test/test_mirroring.py
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@ -0,0 +1,43 @@
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import sys
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from bist import *
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from misoclib.tools.litescope.software.driver.la import LiteScopeLADriver
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def main(wb):
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identifys = []
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generators = []
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checkers = []
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for i in range(4):
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identifys.append(LiteSATABISTIdentifyDriver(wb.regs, "sata_bist{:d}".format(i)))
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generators.append(LiteSATABISTGeneratorDriver(wb.regs, "sata_bist{:d}".format(i)))
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checkers.append(LiteSATABISTCheckerDriver(wb.regs, "sata_bist{:d}".format(i)))
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wb.open()
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regs = wb.regs
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# # #
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print("Identify HDDs:")
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print("-"*80)
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for i, identify in enumerate(identifys):
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identify.run()
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print("HDD{:d}:".format(i))
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print("-"*40)
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identify.hdd_info()
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print("")
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print("Test Mirroring:")
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print("-"*80)
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errors = 0
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for sector in range(8):
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# Write with one generator, verify with all checkers.
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# Use generator number as sector offset to ensure we
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# are not reading data written by another generator.
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for offset, generator in enumerate(generators):
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generator.run(sector + offset, 1024, 1, 1)
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for checker in checkers:
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a, e, s = checker.run(sector + offset, 1024, 1, 1)
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errors += e
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print("errors {:d}".format(errors))
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# # #
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wb.close()
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182
misoclib/mem/litesata/frontend/mirroring.py
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182
misoclib/mem/litesata/frontend/mirroring.py
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@ -0,0 +1,182 @@
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from migen.actorlib.packet import Arbiter, Dispatcher, Status
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from migen.flow.plumbing import Multiplexer
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from misoclib.mem.litesata.common import *
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from misoclib.mem.litesata.frontend.common import *
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from misoclib.mem.litesata.frontend.striping import LiteSATAStripingTX, LiteSATAStripingRX
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class LiteSATAMirroringCtrl(Module):
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def __init__(self, n):
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self.new_cmds = Signal(n)
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self.ack_cmds = Signal(n)
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self.reading = Signal()
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self.writing = Signal()
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self.wants_write = Signal()
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self.write_sel = Signal(max=n)
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# # #
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pending_cmds = Signal(n)
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self.sync += pending_cmds.eq(self.new_cmds | (pending_cmds & ~self.ack_cmds))
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can_commute = Signal()
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self.comb += can_commute.eq((pending_cmds | self.new_cmds) == 0)
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self.fsm = fsm = FSM(reset_state="READ")
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self.submodules += fsm
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fsm.act("READ",
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self.reading.eq(1),
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If(self.wants_write & can_commute,
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NextState("WRITE")
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)
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)
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fsm.act("WRITE",
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self.writing.eq(1),
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If(~self.wants_write & can_commute,
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NextState("READ")
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)
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)
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class LiteSATAMirroringTX(Module):
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def __init__(self, n, dw, ctrl):
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self.sinks = sinks = [Sink(command_tx_description(dw)) for i in range(n)]
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self.sources = sources = [Source(command_tx_description(dw)) for i in range(n)]
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# # #
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wants_write = Signal()
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reading = Signal()
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writing = Signal()
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reads = [Sink(command_tx_description(dw)) for i in range(dw)]
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writes = [Sink(command_tx_description(dw)) for i in range(dw)]
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for sink, read, write in zip(sinks, reads, writes):
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read_stall = Signal()
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read_status = Status(read)
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self.submodules += read_status
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self.comb += [
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Record.connect(sink, read, leave_out=["stb", "ack"]),
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Record.connect(sink, write, leave_out=["stb", "ack"]),
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read.stb.eq(sink.stb & (sink.read | sink.identify) & ~read_stall),
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write.stb.eq(sink.stb & sink.write),
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If(sink.read | sink.identify,
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sink.ack.eq((read.ack & ~read_stall))
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).Else(
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sink.ack.eq(write.ack)
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)
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]
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self.sync += \
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If(~ctrl.wants_write,
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read_stall.eq(0)
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).Elif(~read_status.ongoing,
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read_stall.eq(1)
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)
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write_striper = LiteSATAStripingTX(n, dw, mirroring_mode=True)
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write_arbiter = Arbiter(writes, write_striper.sink)
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self.submodules += write_striper, write_arbiter
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for i in range(n):
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source_status = Status(sources[i])
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self.submodules += source_status
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self.comb += [
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If(ctrl.reading,
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Record.connect(reads[i], sources[i]) # independent reads
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).Elif(ctrl.writing,
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Record.connect(write_striper.sources[i], sources[i]) # identical writes
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),
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ctrl.new_cmds[i].eq(source_status.eop)
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]
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write_striper_sink_status = Status(write_striper.sink)
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self.submodules += write_striper_sink_status
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self.comb += [
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ctrl.wants_write.eq(write_striper_sink_status.ongoing),
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ctrl.write_sel.eq(write_arbiter.rr.grant)
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]
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class LiteSATAMirroringRX(Module):
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def __init__(self, n, dw, ctrl):
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self.sinks = sinks = [Sink(command_rx_description(dw)) for i in range(n)]
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self.sources = sources = [Source(command_rx_description(dw)) for i in range(n)]
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# # #
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muxs = [Multiplexer(command_rx_description(dw), 2) for i in range(n)]
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self.submodules += muxs
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writes = [mux.sink0 for mux in muxs]
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reads = [mux.sink1 for mux in muxs]
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for mux, source in zip(muxs, sources):
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self.comb += [
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mux.sel.eq(ctrl.reading),
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Record.connect(mux.source, source)
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]
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write_striper = LiteSATAStripingRX(n, dw, mirroring_mode=True)
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write_dispatcher = Dispatcher(write_striper.source, writes)
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self.comb += write_dispatcher.sel.eq(ctrl.write_sel)
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self.submodules += write_striper, write_dispatcher
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for i in range(n):
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sink_status = Status(sinks[i])
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self.submodules += sink_status
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self.comb += [
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Record.connect(sinks[i], reads[i], leave_out=["stb", "ack"]),
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Record.connect(sinks[i], write_striper.sinks[i], leave_out=["stb", "ack"]),
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reads[i].stb.eq(sinks[i].stb & ctrl.reading),
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write_striper.sinks[i].stb.eq(sinks[i].stb & ctrl.writing),
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sinks[i].ack.eq(reads[i].ack | write_striper.sinks[i].ack),
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ctrl.ack_cmds[i].eq(sink_status.eop & sinks[i].last)
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]
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class LiteSATAMirroring(Module):
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"""SATA Mirroring
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The mirroring module handles N controllers and provides N ports.
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Each port has its dedicated controller for reads:
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port0 <----> controller0
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portX <----> controllerX
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portN <----> controllerN
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Writes are mirrored on each controller:
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(port0 write) | (portN write)
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port0 ----------+----> controller0 | port0 (stalled) +-----> controller0
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portX (stalled) +----> controllerX | portX (stalled) +-----> controllerX
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portN (stalled) +----> controllerN | portN ----------+-----> controllerN
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Writes have priority on reads. When a write is presented on one of the port, the
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module waits for all ongoing reads to finish and commute to write mode. Once all writes are
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serviced it returns to read mode.
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Characteristics:
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- port's visible capacity = controller's visible capacity
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- total writes throughput = (slowest) controller's throughput
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- total reads throughput = N x controller's throughput
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Can be used for data redundancy and/or to increase total reads speed.
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"""
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def __init__(self, controllers):
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n = len(controllers)
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dw = flen(controllers[0].sink.data)
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self.ports = [LiteSATAUserPort(dw) for i in range(n)]
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# # #
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self.submodules.ctrl = LiteSATAMirroringCtrl(n)
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self.submodules.tx = LiteSATAMirroringTX(n, dw, self.ctrl)
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self.submodules.rx = LiteSATAMirroringRX(n, dw, self.ctrl)
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for i in range(n):
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self.comb += [
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Record.connect(self.ports[i].sink, self.tx.sinks[i]),
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Record.connect(self.tx.sources[i], controllers[i].sink),
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Record.connect(controllers[i].source, self.rx.sinks[i]),
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Record.connect(self.rx.sources[i], self.ports[i].source)
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]
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@ -32,5 +32,8 @@ bist_tb:
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striping_tb:
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$(CMD) striping_tb.py
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mirroring_tb:
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$(CMD) mirroring_tb.py
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clean:
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rm crc scrambler *.vcd
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76
misoclib/mem/litesata/test/mirroring_tb.py
Normal file
76
misoclib/mem/litesata/test/mirroring_tb.py
Normal file
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@ -0,0 +1,76 @@
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from misoclib.mem.litesata.common import *
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from misoclib.mem.litesata.core import LiteSATACore
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from misoclib.mem.litesata.frontend.common import *
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from misoclib.mem.litesata.frontend.crossbar import LiteSATACrossbar
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from misoclib.mem.litesata.frontend.bist import LiteSATABISTGenerator, LiteSATABISTChecker
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from misoclib.mem.litesata.frontend.mirroring import LiteSATAMirroring
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from misoclib.mem.litesata.test.common import *
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from misoclib.mem.litesata.test.model.hdd import *
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class TB(Module):
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def __init__(self):
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self.submodules.hdd0 = HDD(n=0,
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link_debug=False, link_random_level=0,
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transport_debug=False, transport_loopback=False,
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hdd_debug=True)
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self.submodules.core0 = LiteSATACore(self.hdd0.phy)
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self.submodules.hdd1 = HDD(n=1,
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link_debug=False, link_random_level=0,
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transport_debug=False, transport_loopback=False,
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hdd_debug=True)
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self.submodules.core1 = LiteSATACore(self.hdd1.phy)
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self.submodules.mirroring = LiteSATAMirroring([self.core0, self.core1])
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self.submodules.crossbar0 = LiteSATACrossbar(self.mirroring.ports[0])
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self.submodules.generator0 = LiteSATABISTGenerator(self.crossbar0.get_port())
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self.submodules.checker0 = LiteSATABISTChecker(self.crossbar0.get_port())
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self.submodules.crossbar1 = LiteSATACrossbar(self.mirroring.ports[1])
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self.submodules.generator1 = LiteSATABISTGenerator(self.crossbar1.get_port())
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self.submodules.checker1 = LiteSATABISTChecker(self.crossbar1.get_port())
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def gen_simulation(self, selfp):
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hdd0 = self.hdd0
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hdd0.malloc(0, 64)
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hdd1 = self.hdd1
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hdd1.malloc(0, 64)
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sector = 0
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count = 1
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checker0 = selfp.checker0
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checker1 = selfp.checker1
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while True:
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for generator in [selfp.generator0, selfp.generator1]:
|
||||
# write data (alternate generators)
|
||||
generator.sector = sector
|
||||
generator.count = count
|
||||
generator.start = 1
|
||||
yield
|
||||
generator.start = 0
|
||||
yield
|
||||
while generator.done == 0:
|
||||
yield
|
||||
|
||||
# verify data on the 2 hdds in //
|
||||
checker0.sector = sector
|
||||
checker0.count = count
|
||||
checker0.start = 1
|
||||
checker1.sector = sector
|
||||
checker1.count = count
|
||||
checker1.start = 1
|
||||
yield
|
||||
checker0.start = 0
|
||||
checker1.start = 0
|
||||
yield
|
||||
while (checker0.done == 0) or (checker1.done == 0):
|
||||
yield
|
||||
print("errors {}".format(checker0.errors + checker1.errors))
|
||||
|
||||
# prepare next iteration
|
||||
sector += 1
|
||||
|
||||
if __name__ == "__main__":
|
||||
run_simulation(TB(), ncycles=4096, vcd_name="my.vcd", keep_files=True)
|
||||
Loading…
Reference in a new issue