Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

dvisampler/chansync: use Record.raw_bits()

Browse source
This commit is contained in:
Sebastien Bourdeauducq 2013-04-14 17:06:29 +02:00
parent 8914969760
commit 0d21711c1b
1 changed files with 2 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
milkymist/dvisampler/chansync.py
View file

@ -31,8 +31,8 @@ class ChanSync(Module, AutoCSR):
self.add_submodule(fifo, "pix") self.add_submodule(fifo, "pix")
self.comb += [ self.comb += [
fifo.we.eq(self.valid_i), fifo.we.eq(self.valid_i),
fifo.din.eq(Cat(*data_in.flatten())), fifo.din.eq(data_in.raw_bits()),
Cat(*data_out.flatten()).eq(fifo.dout) data_out.raw_bits().eq(fifo.dout)
] ]
is_control = Signal() is_control = Signal()
is_control_r = Signal() is_control_r = Signal()