litesata/core/link: move buffer on CONTInserter (seems better for timings when set on sink)

2015-05-25 13:55:15 +02:00 · 2015-05-25 13:55:15 +02:00 · 0d2db23603
parent cb053dc011
commit 0d2db23603
1 changed files with 1 additions and 1 deletions
--- a/misoclib/mem/litesata/core/link/init.py
+++ b/misoclib/mem/litesata/core/link/init.py
@ -36,7 +36,7 @@ class LiteSATALinkTX(Module):

        # inserter CONT and scrambled data between
        # CONT and next primitive
-        cont = BufferizeEndpoints("source")(LiteSATACONTInserter(phy_description(32)))
+        cont = BufferizeEndpoints("sink")(LiteSATACONTInserter(phy_description(32)))
        self.submodules += cont

        # datas / primitives mux