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litesata/core/link: move buffer on CONTInserter (seems better for timings when set on sink)

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Florent Kermarrec 2015-05-25 13:55:15 +02:00
parent cb053dc011
commit 0d2db23603
1 changed files with 1 additions and 1 deletions
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2
misoclib/mem/litesata/core/link/__init__.py
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@ -36,7 +36,7 @@ class LiteSATALinkTX(Module):
# inserter CONT and scrambled data between
# CONT and next primitive
cont = BufferizeEndpoints("source")(LiteSATACONTInserter(phy_description(32)))
cont = BufferizeEndpoints("sink")(LiteSATACONTInserter(phy_description(32)))
self.submodules += cont
# datas / primitives mux