tools/litex_sim_new: remove
This commit is contained in:
Florent Kermarrec
parent
21d38701df
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0d7430fc69
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#!/usr/bin/env python3
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# This file is Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2020 Piotr Binkowski <pbinkowski@antmicro.com>
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# This file is Copyright (c) 2017 Pierre-Olivier Vauboin <po@lambdaconcept>
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# License: BSD
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import argparse
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from migen import *
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from litex.build.generic_platform import *
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from litex.build.sim import SimPlatform
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from litex.build.sim.config import SimConfig
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from litex.soc.integration.common import *
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from litex.soc.integration.soc import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.cores import uart
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from litedram import modules as litedram_modules
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from litedram.common import *
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from litedram.phy.model import SDRAMPHYModel
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from liteeth.phy.model import LiteEthPHYModel
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from liteeth.mac import LiteEthMAC
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from liteeth.core import LiteEthUDPIPCore
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from liteeth.frontend.etherbone import LiteEthEtherbone
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from litescope import LiteScopeAnalyzer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("sys_clk", 0, Pins(1)),
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("sys_rst", 0, Pins(1)),
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("serial", 0,
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Subsignal("source_valid", Pins(1)),
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Subsignal("source_ready", Pins(1)),
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Subsignal("source_data", Pins(8)),
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Subsignal("sink_valid", Pins(1)),
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Subsignal("sink_ready", Pins(1)),
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Subsignal("sink_data", Pins(8)),
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),
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("eth_clocks", 0,
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Subsignal("tx", Pins(1)),
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Subsignal("rx", Pins(1)),
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),
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("eth", 0,
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Subsignal("source_valid", Pins(1)),
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Subsignal("source_ready", Pins(1)),
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Subsignal("source_data", Pins(8)),
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Subsignal("sink_valid", Pins(1)),
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Subsignal("sink_ready", Pins(1)),
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Subsignal("sink_data", Pins(8)),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(SimPlatform):
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def __init__(self):
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SimPlatform.__init__(self, "SIM", _io)
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# DFI PHY model settings ---------------------------------------------------------------------------
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sdram_module_nphases = {
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"SDR": 1,
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"DDR": 2,
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"LPDDR": 2,
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"DDR2": 2,
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"DDR3": 4,
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"DDR4": 4,
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}
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def get_sdram_phy_settings(memtype, data_width, clk_freq):
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nphases = sdram_module_nphases[memtype]
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if memtype == "SDR":
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# Settings from gensdrphy
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rdphase = 0
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wrphase = 0
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rdcmdphase = 0
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wrcmdphase = 0
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cl = 2
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cwl = None
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read_latency = 4
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write_latency = 0
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elif memtype in ["DDR", "LPDDR"]:
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# Settings from s6ddrphy
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rdphase = 0
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wrphase = 1
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rdcmdphase = 1
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wrcmdphase = 0
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cl = 3
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cwl = None
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read_latency = 5
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write_latency = 0
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elif memtype in ["DDR2", "DDR3"]:
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# Settings from s7ddrphy
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tck = 2/(2*nphases*clk_freq)
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cmd_latency = 0
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cl, cwl = get_cl_cw(memtype, tck)
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cl_sys_latency = get_sys_latency(nphases, cl)
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cwl = cwl + cmd_latency
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cwl_sys_latency = get_sys_latency(nphases, cwl)
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rdcmdphase, rdphase = get_sys_phases(nphases, cl_sys_latency, cl)
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wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl)
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read_latency = 2 + cl_sys_latency + 2 + 3
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write_latency = cwl_sys_latency
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elif memtype == "DDR4":
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# Settings from usddrphy
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tck = 2/(2*nphases*clk_freq)
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cmd_latency = 0
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cl, cwl = get_cl_cw(memtype, tck)
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cl_sys_latency = get_sys_latency(nphases, cl)
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cwl = cwl + cmd_latency
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cwl_sys_latency = get_sys_latency(nphases, cwl)
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rdcmdphase, rdphase = get_sys_phases(nphases, cl_sys_latency, cl)
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wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl)
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read_latency = 2 + cl_sys_latency + 1 + 3
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write_latency = cwl_sys_latency
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sdram_phy_settings = {
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"nphases": nphases,
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"rdphase": rdphase,
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"wrphase": wrphase,
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"rdcmdphase": rdcmdphase,
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"wrcmdphase": wrcmdphase,
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"cl": cl,
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"cwl": cwl,
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"read_latency": read_latency,
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"write_latency": write_latency,
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}
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return PhySettings(
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memtype = memtype,
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databits = data_width,
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dfi_databits = data_width if memtype == "SDR" else 2*data_width,
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**sdram_phy_settings,
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)
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# Simulation SoC -----------------------------------------------------------------------------------
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class SimSoC(SoCCore):
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mem_map = {
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"ethmac": 0xb0000000,
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}
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mem_map.update(SoCCore.mem_map)
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def __init__(self,
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with_sdram = False,
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with_ethernet = False,
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with_etherbone = False,
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etherbone_mac_address = 0x10e2d5000000,
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etherbone_ip_address = "192.168.1.50",
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with_analyzer = False,
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sdram_module = "MT48LC16M16",
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sdram_init = [],
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sdram_data_width = 32,
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**kwargs):
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platform = Platform()
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sys_clk_freq = int(1e6)
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# SoCCore ---------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
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ident = "LiteX Simulation", ident_version=True,
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with_uart = False,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = CRG(platform.request("sys_clk"))
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# Serial -----------------------------------------------------------------------------------
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self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial"))
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self.submodules.uart = uart.UART(self.uart_phy)
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self.csr.add("uart")
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self.irq.add("uart")
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# SDRAM ------------------------------------------------------------------------------------
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if with_sdram:
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sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings
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sdram_module_cls = getattr(litedram_modules, sdram_module)
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sdram_rate = "1:{}".format(sdram_module_nphases[sdram_module_cls.memtype])
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sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate)
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phy_settings = get_sdram_phy_settings(
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memtype = sdram_module.memtype,
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data_width = sdram_data_width,
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clk_freq = sdram_clk_freq)
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self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings, init=sdram_init)
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = sdram_module,
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origin = self.mem_map["main_ram"]
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)
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# Reduce memtest size for simulation speedup
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self.add_constant("MEMTEST_DATA_SIZE", 8*1024)
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self.add_constant("MEMTEST_ADDR_SIZE", 8*1024)
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assert not (with_ethernet and with_etherbone)
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# Ethernet ---------------------------------------------------------------------------------
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if with_ethernet:
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# Ethernet PHY
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self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0))
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self.csr.add("ethphy")
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# Ethernet MAC
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ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
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interface = "wishbone",
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endianness = self.cpu.endianness)
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self.submodules.ethmac = ethmac
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self.bus.add_slave("ethmac", self.ethmac.bus, SoCRegion(size=0x2000, cached=False))
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self.csr.add("ethmac")
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self.irq.add("ethmac")
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# Etherbone --------------------------------------------------------------------------------
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if with_etherbone:
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# Ethernet PHY
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self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0)) # FIXME
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self.csr.add("ethphy")
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# Ethernet Core
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ethcore = LiteEthUDPIPCore(self.ethphy,
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mac_address = etherbone_mac_address,
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ip_address = etherbone_ip_address,
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clk_freq = sys_clk_freq)
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self.submodules.ethcore = ethcore
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# Etherbone
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self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master")
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self.bus.add_master(master=self.etherbone.wishbone.bus)
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# Analyzer ---------------------------------------------------------------------------------
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if with_analyzer:
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analyzer_signals = [
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self.cpu.ibus,
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self.cpu.dbus
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]
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self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
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self.csr.add("analyzer")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="Generic LiteX SoC Simulation")
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builder_args(parser)
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soc_sdram_args(parser)
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parser.add_argument("--threads", default=1, help="Set number of threads (default=1)")
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parser.add_argument("--rom-init", default=None, help="rom_init file")
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parser.add_argument("--ram-init", default=None, help="ram_init file")
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parser.add_argument("--with-sdram", action="store_true", help="Enable SDRAM support")
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parser.add_argument("--sdram-module", default="MT48LC16M16", help="Select SDRAM chip")
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parser.add_argument("--sdram-data-width", default=32, help="Set SDRAM chip data width")
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parser.add_argument("--sdram-init", default=None, help="SDRAM init file")
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parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
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parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
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parser.add_argument("--with-analyzer", action="store_true", help="Enable Analyzer support")
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parser.add_argument("--trace", action="store_true", help="Enable VCD tracing")
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parser.add_argument("--trace-start", default=0, help="Cycle to start VCD tracing")
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parser.add_argument("--trace-end", default=-1, help="Cycle to end VCD tracing")
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parser.add_argument("--opt-level", default="O3", help="Compilation optimization level")
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args = parser.parse_args()
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soc_kwargs = soc_sdram_argdict(args)
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builder_kwargs = builder_argdict(args)
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sim_config = SimConfig(default_clk="sys_clk")
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sim_config.add_module("serial2console", "serial")
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# Configuration --------------------------------------------------------------------------------
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cpu_endianness = "little"
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if "cpu_type" in soc_kwargs:
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if soc_kwargs["cpu_type"] in ["mor1kx", "lm32"]:
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cpu_endianness = "big"
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if args.rom_init:
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soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, cpu_endianness)
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if not args.with_sdram:
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soc_kwargs["integrated_main_ram_size"] = 0x10000000 # 256 MB
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if args.ram_init is not None:
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soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init, cpu_endianness)
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else:
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assert args.ram_init is None
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soc_kwargs["integrated_main_ram_size"] = 0x0
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soc_kwargs["sdram_module"] = args.sdram_module
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soc_kwargs["sdram_data_width"] = int(args.sdram_data_width)
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if args.with_ethernet or args.with_etherbone:
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sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"})
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# SoC ------------------------------------------------------------------------------------------
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soc = SimSoC(
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with_sdram = args.with_sdram,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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with_analyzer = args.with_analyzer,
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sdram_init = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu_endianness),
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**soc_kwargs)
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if args.ram_init is not None:
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soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
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# Build/Run ------------------------------------------------------------------------------------
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builder_kwargs["csr_csv"] = "csr.csv"
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builder = Builder(soc, **builder_kwargs)
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vns = builder.build(run=False, threads=args.threads, sim_config=sim_config,
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opt_level=args.opt_level,
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trace=args.trace, trace_start=int(args.trace_start), trace_end=int(args.trace_end))
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if args.with_analyzer:
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soc.analyzer.export_csv(vns, "analyzer.csv")
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builder.build(build=False, threads=args.threads, sim_config=sim_config,
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opt_level = args.opt_level,
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trace = args.trace,
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trace_start = int(args.trace_start),
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trace_end = int(args.trace_end)
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)
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if __name__ == "__main__":
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main()
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