copy README chapters to .rst

README

@@ -62,7 +62,7 @@ Frontend:
 
 [> Possibles improvements
 ----------------------
-- add standardized adapters (AXI, Avalon-ST)
+- add standardized interfaces (AXI, Avalon-ST)
 - add NCQ support
 - add AES hardware encryption
 - add on-the-flow compression/decompression

doc/source/docs/getting_started/downloads.rst

@@ -3,3 +3,28 @@
 ====================
 Download and install
 ====================
+1. Install Python3 and Xilinx's Vivado software
+
+2. Obtain Migen and install it:
+  - git clone https://github.com/enjoy-digital/migen
+  - cd migen
+  - python3 setup.py install
+  - cd ..
+
+3. Obtain Miscope and install it:
+  - git clone https://github.com/enjoy-digital/miscope
+  - cd miscope
+  - python3 setup.py install
+  - cd ..
+
+4. Obtain MiSoC:
+  - git clone https://github.com/enjoy-digital/misoc --recursive
+
+5. Copy lite-sata in working directory and move to it.
+
+6. Build and load design:
+  - python3 make.py all
+
+7. Test design:
+  - go to test directory and run:
+  - python3 bist.py

doc/source/docs/getting_started/index.rst

@@ -7,3 +7,10 @@ Getting Started
 Now you know why LiteSATA is :ref:`core for you <about-litesata>`, it's time to *get started*.
 
 This section provides a walk-through of :ref:`downloading and installing the tools`.
+
+.. toctree::
+	:maxdepth: 1
+
+	downloads
+	FAQ
+

doc/source/docs/introducing_litesata/about_litesata.rst

@@ -55,3 +55,18 @@ Frontend:
   - Configurable crossbar (simply use core.crossbar.get_port() to add a new port!)
   - Ports arbitration transparent to the user
   - Synthetizable BIST
+
+
+Possibles improvements
+====================
+- add standardized interfaces (AXI, Avalon-ST)
+- add NCQ support
+- add AES hardware encryption
+- add on-the-flow compression/decompression
+- add support for Altera PHYs.
+- add support for Lattice PHYs.
+- add support for Xilinx 7-Series GTP/GTH (currently only 7-Series GTX are
+  supported)
+- add Zynq Linux drivers.
+- ...
+

doc/source/docs/introducing_litesata/litesata_license.rst

@@ -4,3 +4,13 @@
 Open Source License
 ===================
 
+LiteSATA is released under the very permissive two-clause BSD license. Under the
+terms of this license, you are authorized to use Migen for closed-source
+proprietary designs.
+Even though we do not require you to do so, those things are awesome, so please
+do them if possible:
+ - tell us that you are using LiteSATA
+ - cite Migen in publications related to research it has helped
+ - send us feedback and suggestions for improvements
+ - send us bug reports when something goes wrong
+ - send us the modifications and improvements you have done to LiteSATA.

doc/source/docs/simulation/index.rst

@@ -3,3 +3,15 @@
 ========================
 Simulation
 ========================
+
+Simulations are avalaible in ./lib/sata/test:
+  - crc_tb
+  - scrambler_tb
+  - phy_datapath_tb
+  - link_tb
+  - command_tb
+  - bist_tb
+
+hdd.py is a simplified HDD model implementing all SATA layers.
+To run a simulation, move to ./lib/sata/test and run:
+  - make simulation_name

doc/source/docs/test/index.rst

@@ -3,3 +3,8 @@
 ========================
 Test
 ========================
+
+A synthetisable BIST is provided and can be controlled with ./test/bist.py.
+By using Miscope and the provided ./test/test_link.py example you are able to
+visualize the internal logic of the design and even inject the captured data in
+the HDD model!