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Multiply system clock

This commit is contained in:
Sebastien Bourdeauducq 2011-12-17 15:00:18 +01:00
parent 85fbe07b94
commit 0e30d67fa3
2 changed files with 15 additions and 8 deletions
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6
constraints.py
View File

@ -1,4 +1,4 @@
def get(ns, reset0, norflash0, uart0): def get(ns, clkfx_sys, reset0, norflash0, uart0):
constraints = [] constraints = []
def add(signal, pin, vec=-1, iostandard="LVCMOS33", extra=""): def add(signal, pin, vec=-1, iostandard="LVCMOS33", extra=""):
constraints.append((ns.get_name(signal), vec, pin, iostandard, extra)) constraints.append((ns.get_name(signal), vec, pin, iostandard, extra))
@ -8,6 +8,8 @@ def get(ns, reset0, norflash0, uart0):
add(signal, p, i, iostandard, extra) add(signal, p, i, iostandard, extra)
i += 1 i += 1
add(clkfx_sys.clkin, "AB11", extra="TNM_NET = \"GRPclk50\"")
add(reset0.trigger_reset, "AA4") add(reset0.trigger_reset, "AA4")
add(reset0.ac97_rst_n, "D6") add(reset0.ac97_rst_n, "D6")
add(reset0.videoin_rst_n, "W17") add(reset0.videoin_rst_n, "W17")
@ -39,8 +41,6 @@ def get(ns, reset0, norflash0, uart0):
r += ";\n" r += ";\n"
r += """ r += """
NET "sys_clk" LOC = AB11 | IOSTANDARD = LVCMOS33;
NET "sys_clk" TNM_NET = "GRPclk50";
TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%; TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
""" """

17
top.py
View File

@ -2,10 +2,14 @@ from migen.fhdl.structure import *
from migen.fhdl import convtools, verilog, autofragment from migen.fhdl import convtools, verilog, autofragment
from migen.bus import wishbone, csr, wishbone2csr from migen.bus import wishbone, csr, wishbone2csr
from milkymist import m1reset, lm32, norflash, uart from milkymist import m1reset, clkfx, lm32, norflash, uart
import constraints import constraints
def get(): def get():
MHz = 1000000
clk_freq = 80*MHz
clkfx_sys = clkfx.Inst(50*MHz, clk_freq)
reset0 = m1reset.Inst() reset0 = m1reset.Inst()
cpu0 = lm32.Inst() cpu0 = lm32.Inst()
@ -16,13 +20,16 @@ def get():
[(0, norflash0.bus), (3, wishbone2csr0.wishbone)], [(0, norflash0.bus), (3, wishbone2csr0.wishbone)],
register=True, register=True,
offset=1) offset=1)
uart0 = uart.Inst(0, 50*1000*1000, baud=115200) uart0 = uart.Inst(0, clk_freq, baud=115200)
csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bus]) csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bus])
frag = autofragment.from_local() + Fragment(pads={reset0.trigger_reset}) frag = autofragment.from_local()
vns = convtools.Namespace() vns = convtools.Namespace()
src_verilog = verilog.Convert(frag, name="soc", src_verilog = verilog.Convert(frag,
{clkfx_sys.clkin, reset0.trigger_reset},
name="soc",
clk_signal=clkfx_sys.clkout,
rst_signal=reset0.sys_rst, rst_signal=reset0.sys_rst,
ns=vns) ns=vns)
src_ucf = constraints.get(vns, reset0, norflash0, uart0) src_ucf = constraints.get(vns, clkfx_sys, reset0, norflash0, uart0)
return (src_verilog, src_ucf) return (src_verilog, src_ucf)